Improved design supports Samsung's latest foundry processes

This enablement includes delivery of comprehensive Process Design Kits (PDKs) that include routing rules, physical verification runsets for DRC and LVS, signoff-accurate extraction technology files and SPICE models for 8LPP and 7LPP process technologies.

Anchored by IC Compiler II and Design Compiler Graphical, the complete physical implementation solution has been enabled with new design rules for 8LPP and 7LPP process technologies.

The platform supports sophisticated multi-patterning requirements for the 8LPP process. It has been enhanced for 7LPP to handle extreme ultraviolet (EUV) single pattern-based routing and power network via stapling for improved reliability.

"Built on a long history of deep collaboration with Synopsys, platform enablement allows our mutual customers to design the most competitive 8LPP and 7LPP system on chip (SoC) products," said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics.

"Our foundry customers can rapidly and confidently ramp their designs to volume production on all of our advanced FinFET-based processes using the Synopsys Design Platform."

"Our collaboration with Samsung Foundry is focused on enabling designers to get the optimum QoR on Samsung Foundry's most advanced FinFET process technologies," said Michael Jackson, corporate vice president of marketing and business development for Synopsys' Design Group. "With tapeouts already completed, our mutual customers can confidently deploy Synopsys Design Platform for their 8LPP or 7LPP SoC designs."

Synopsys Design Platform PDKs are available from Samsung for early access engagements. Key tools and features of the Synopsys Design Platform enabled for 8LPP and 7LPP process technologies include:

• IC Compiler II place and route solution: Single through multi-pattern and color-aware physical implementation
• Design Compiler Graphical RTL synthesis: Correlation, congestion reduction, and physical guidance for IC Compiler II
• IC Validator signoff physical verification: In-Design, automated single through multi-patterning DRC repair, DFM pattern matching and DFM metal fill within IC Compiler II place-and-route system; and LVS signoff
• StarRC extraction: Single through multi-patterning, full color-aware variation and 3D FinFET modeling
• HSPICE simulation: Device modeling with self-heating effect and accurate simulation of analog, high-frequency and SRAM designs