imec and Cadence have announced that the two companies have completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography. To produce this test chip, imec and Cadence optimised design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence Innovus Implementation System.
Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.
The Innovus Implementation System is a next-gen physical implementation solution that enables SoC developers to deliver designs with best-in-class PPA while accelerating time to market. Driven by a massively parallel architecture with breakthrough optimization technologies, the Innovus Implementation System provides typically 10 to 20 better PPA and up to ten times full-flow speedup and capacity gain.
“Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries including 5nm and below,” said An Steegen, Senior Vice President, Process Technology, imec. “Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip. The Cadence next-gen platform is easy to use, which helps our engineering team stay productive in developing the rule set for advanced nodes.”
“By achieving this milestone, Cadence and imec continue to demonstrate our dedication toward pushing patterning technologies to increasingly smaller nodes,” said Dr. Anirudh Devgan, Senior Vice President and General Manager, Digital and Signoff Group, Cadence. “With imec technology and the Cadence Innovus Implementation System, we’ve created a working flow that can pave the way for developing innovative next-generation mobile and computer advanced-node designs.”