IC Compiler II for next-gen communications network design

15th July 2019
Posted By : Lanna Cooper
IC Compiler II for next-gen communications network design

Synopsys has announced immediate availability of the latest release of its flagship IC Compiler II place-and-route system that includes several new innovative technologies to deliver Quality-of-Results (QoR) and fastest Time-To-Results (TTR) for the next wave of designs across a wide range of vertical markets, including automotive, cloud computing, AI, networking and wireless applications.

Continued investment in technology advancements in IC Compiler II technologies deliver ten percent total power reduction, five percent smaller area, five percent better timing, and a two times faster run time. Based on observed benefits, Realtek has deployed the latest IC Compiler II technologies on their next-gen communication network designs to meet stringent Power, Performance, and Area (PPA) budgets while speeding up TTR for their designs.

"Designing some of the most complex network communications devices and achieving the highest QoR without compromising our design schedule is absolutely critical for us in our target markets," said Realtek's Vice President and Spokesman, Yee-Wei Huang. "We have collaborated closely with Synopsys in deploying the latest IC Compiler II technologies and have observed up to two times run time speed-up. We are confident that we can effectively meet our aggressive QoR and time-to-market goals."

Key new technologies in IC Compiler II for QoR include a common physical optimisation infrastructure, new arc-based unified Concurrent Clock-and-Data (CCD) optimisation, physically-aware logic re-synthesis, and dynamic voltage drop-driven power shaping. RedHawk Analysis Fusion IR drop-driven optimisation, exhaustive Path-Based Analysis (PBA), and signoff accuracy within IC Compiler II result in unmatched design convergence.

Several new speed-up improvements, including inherent core engine algorithm speed-up, intelligent scenario management, efficient hardware scaling, and flow concurrency, deliver two times faster design throughput.

"The IC Compiler II place-and-route solution is the preferred tool of choice for complex next-generation designs where pushing PPA boundaries is critical," said Sassine Ghazi, General Manager of the Design Group at Synopsys. "Customers like Realtek are at the forefront of innovation, and their adoption of the latest IC Compiler II release is a testament to how Synopsys' place-and-route solution is leading the industry in QoR and helping them deliver differentiated products."


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