Helping to reduce design time

3rd March 2016
Posted By : Joe Bush
Helping to reduce design time

A mixed signal low power flow from Cadence Design Systems has been employed by Silicon Labs to reduce overall design time, significantly speeding time to market. Silicon Labs adopted the flow for its new Blue Gecko family of wireless system-on-chip (SoC) devices that provide ultra-low power Bluetooth Smart connectivity for Internet of Things (IoT) applications.

For design, Silicon Labs used the Cadence mixed signal, low power flow based on the unified OpenAccess (OA) enabled Incremental Technology Database (ITDB) to seamlessly interoperate between the Cadence Virtuoso analogue platform and the Cadence digital implementation suite of tools.

For mixed signal verification, Silicon Labs adopted the Cadence Spectre Multi-Mode Simulation (MMSIM) solution, which improved productivity by up to 3X, helped reduce power consumption and extended the connectivity range of the Blue Gecko SoCs with high performance. The mixed mode, full chip functional simulation enabled by Incisive Enterprise Simulator with its DMS Option accelerated Silicon Labs’ design verification by up to 10X, compared to transistor or device level simulation options.


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