In order to address the challenges of designing and verifying Fan-Out Chip-on-substrate (FOCos) multi-die packages, Advanced Semiconductor Engineering and Cadence Design Systems have collaborated to release a System-in-Package (SiP) EDA solution. The solution consists of the SiP-id (System-in-Package - intelligent design) design kit, an enhanced reference flow including IC packaging and verification tools from Cadence, and a new methodology that aggregates the requirements of wafer-, package- and system-level design into a unified and automated flow.
By deploying the SiP-id methodology, designers can reduce design iterations and greatly improve throughput as compared to existing advanced packaging EDA tools, reducing the time needed to design and verify ultra-complex SiP packages.
In today’s smart world, innovators are on the front line, designing devices that pack greater functionality, generate higher and faster performance, and consume lower power, all while being integrated within shrinking space parameters. As a result, the role of IC packaging in electronics has never been more important than now. Technology has become an integral part of daily life, with global proliferation of smartphones and wearables, and significant application strides in artificial intelligence, autonomous vehicles and the IoT. These developments have created immense opportunity for ASE to apply its SiP technology beyond package level to module-, board- and system-level integration.
Previously, IC packaging engineers leveraged standard EDA design tools coupled with a set of loosely defined rules to lay out their packages. However, this approach has many limitations when designing today’s advanced multi-die packages. To provide a more holistic approach to the design and verification of SiP and advanced fan- out packages, ASE and Cadence collaborated closely to develop a design kit, methodology, and streamlined and automated reference flow using enhanced Cadence IC packaging and verification tools, all tailored for ASE’s advanced IC package technologies. In a typical use case with high-pin-count dies, packaging engineers using SiP-id and the accompanying reference flow and methodology were able to reduce time from more than six hours to only 17 minutes, compared to existing tools with manual operation.
“As the leader in System-in-Package technology, ASE has been augmenting our design and manufacturing services by building a SiP ecosystem with partners across the entire supply chain including EDA providers,” said C. P. Hung, Vice President, Corporate R&D, ASE Group. “SiP-id is a prime example of the successful collaboration between ASE and Cadence that achieved optimal results through the mutual sharing of technology and experiences. Ultimately, we aim to offer our customers a set of efficient EDA tools to design more complex chips using ASE’s advanced package and system-level technologies and help them speed up time to market,” he added.
“More and more of our customers are looking at multi-die advanced-package technologies to solve their next-gen design challenges,” said Tom Beckley, Senior Vice President and General Manager of the Custom IC & PCB Group at Cadence. “Advanced packaging extends Moore’s Law and plays directly into our System Design Enablement strategy, so collaborating with ASE to fulfill their vision for SiP is a natural fit for us. We expect the results of this effort to mutually benefit Cadence and ASE customers by providing a methodology optimised for SiP design.”