Electronic design verification company, Aldec, has expanded the rule-checking capabilities of its ALINT-PRO tool in response to growing complexity of large-scale modern FPGA and ASIC designs. Rules new to the 2017.12 release of ALINT-PRO assure the integrity of a design’s Finite State Machines (FSMs) and help identify possible Reset Domain Crossing (RDC) issues.
“In large designs it is typical to have several FSMs controlling the workflow. However, despite the use of consistent HDL patterns to describe the FSMs, the number of coding mistakes made in the RTL descriptions is often high,” observed Sergei Zaychenko, Aldec Software Product Manager. “At Aldec, we are aiming to provide the most comprehensive rule coverage to help designers create reliable, portable, and highly readable state machine descriptions.”
Verification of RDCs, also new to the 2017.12 release of ALINT-PRO, targets issues with complex SoC reset strategies and circuits with dynamically switchable regions. For instance, a harmless looking data transfer between registers with unrelated asynchronous reset controls may end with unrecoverable metastability, unless properly addressed at the RTL design phase.