CoWare and Tenison work together on Virtual Hardware Platforms for Architectural Exploration and Software Development

23rd January 2007
Posted By : ES Admin
CoWare and Tenison Design Automation Inc., a company focused on delivering ESL tools that synthesize C++ and SystemC models from hardware designs described in Verilog or VHDL, jointly announced significant enhancements to the two companies' integrated design flow. These enhancements will accelerate the creation of virtual hardware platforms for architectural exploration and software development. The new flow enables the synthesis of the CoWare SystemC Modeling Library (SCML)-based peripheral models from legacy RTL IP, thus accelerating model availability for product architects and software developers using CoWare Platform Architect and CoWare Virtual Platforms.
SoC developers recognize that higher reuse and standards-based model interoperability are strategically important to realizing the return on their ESL investment, said A.K. Kalekos, vice-president marketing and business development, CoWare. Together with Tenison VTOC®, CoWare's
platform-driven ESL design solutions and standards-based SCML provide our customers with a valuable combination that complements new SystemC model development initiatives with the ability to efficiently tap into their existing portfolio of legacy RTL.

The new transaction-level integration between CoWare Platform Architect and Tenison VTOC takes advantage of CoWare's standards-based SCML to enable Tenison VTOC to synthesize highly reusable SystemC models from legacy Verilog and VHDL RTL code.

In addition, the flow supports Tenison's VTRAC transactor technology which enables the VTOC portion of the platform model to run more efficiently and only when it is active in the system simulation, thus leveraging the capabilities of CoWare high performance simulation technology.

Architecture exploration and software development tasks can begin simultaneously with all components of the design - both native SCML functions written in SystemC and VTOC SCML functions synthesized from legacy RTL designs - treated as peers within the platform assembly and debugging environment. This reduces development time by enabling initial platform models to be assembled sooner, without the need to code all the platform components by hand.

Seventy percent of most systems-on-chip and system designs are reused IP and improving the availability of all the IP models required by a virtual hardware platform greatly relieves the immense schedule pressure felt by engineering managers, said Martin Harding, president and CEO, Tenison
Design Automation. Our new VTOC flow, with CoWare Platform Architect and CoWare Virtual Platform, allows the legacy IP needed to complete the platform for architecture exploration and software development to be imported without a remodeling effort. This saves time and frees engineers
to focus on development of new functions that don't yet exist in RTL.

Optimization of high-bandwidth peripheral components in native SystemC can be performed in parallel as a further refinement. This means that now the bulk of the development time can be focused on modeling new components, exploring the platform architecture, and validating the model for early
software development with the same native SCML debug visibility for all components in the platform.

CoWare Platform Architect and SCML are available today. Tenison VTOC with automated CoWare SCML integration is available for select customers today, with general availability in Q2 2007. CoWare and Tenison will demonstrate the joint integration in booths #2 and #232 (Emerging Companies Area),
respectively, at the 2007 Electronic Design Solutions Fair to be held this week on January 25 and 26 in Yokohama, Japan.

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