The profitability of complex SoC projects could be doubled by Engineering teams, whilst also reducing their development costs by a quarter by improving their debug and monitoring strategy, according to a new white paper published by Semico Research in association with UltraSoC.
The white paper considers the increasing cost and complexity of SoC design, and includes a detailed analysis of typical engineering costs in areas from architectural design through validation, verification and bring-up. It then calculates the impact of time-to-market acceleration on shipment volumes, ASPs, overall revenue and profitability, for a typical SoC over a 24 month market window.
UltraSoC CEO Rupert Baines commented: “Hardware-based monitoring and debug is usually treated as a minor technical issue. But what Semico’s independent analysis reveals is a real business impact: on costs, on revenue and on profit. It’s why we’re convinced that this is an issue for the CFO and general management, as well as for engineering. This white paper supports that argument with hard numbers and solid analysis based on Semico’s extensive knowledge of real world SoC design projects.”
Semico’s research compares two SoC development teams undertaking similar designs, with or without the use of on-chip debug and monitoring technology. It reveals a 27% reduction in the total cost of a SoC development project, and 2.3 times uplift in profitability over the typical 24 month market window, due mainly to accelerated market entry, increased shipment volumes and improved ASPs.
According to Semico, even after the design is complete and the SoC is shipped, on-chip monitoring and debug brings further benefits, because it dramatically reduces the cost of finding a bug in the system once it has entered the market and is in the field. The same technology can also be used for gathering real usage data and in-life performance optimisation.
Modern verification tools are so good that silicon-level bugs are rare. However, such tools do not help at the system level. Today’s SoCs are so complex, often with multiple cores, hierarchical interconnects and many sub-systems, that bugs arise from their interactions. Blocks that are correct at unit test fail because of the dependencies that only emerge in real silicon at run time. UltraSoC’s embedded debug IP helps identify these subtle problems arising from systemic complexity post-silicon, in bring-up and in the field.