Clock reference design for RADAR and 5G wireless testers

This reference design supports scaling up JESD204B synchronised clocks in daisy chain configuration.

This design provides multichannel JESD204B clocks using TI’s LMK04828 clock jitter cleaner and LMX2594 wideband PLL with integrated VCOs to achieve clock-to-clock skew of less than 10ps.

This design is tested with TI’s ADC12DJ3200 EVMs at 3 GSPS, and a channel-to-channel skew of less than 50ps is achieved with improved SNR performance.

All key design theories are described to guide users through the part selection process and design optimisation. Finally, schematics, board layouts, hardware testing, and test results are included.

Features

• High frequency (GSPS) sample clock generation
• High channel count and scalable JESD204B compliant clock solution
• Low phase noise clocking for RF sampling ADC/DAC
• Configurable phase synchronisation to achieve low skew in multi-channel system
• Supports TI’s high speed converter and capture cards (ADC12DJ3200EVM, TSW14J56 / TSW14J57)

For more information, click here.