A collaboration between Cadence Design Systems and Arm has been announced to enable high-performance computing (HPC) customers to execute bare metal pre-silicon verification compliance tests through the Arm Server Base System Architecture (SBSA) Compliance Suite.
This will be done by using the Palladium Z1 Enterprise Emulation Platform and Perspec System Verifier from the Cadence Verification Suite. Through the collaboration, customers can now perform compliance testing on Arm-based server systems-on-chip (SoCs) up to three months prior to Linux bring-up, shortening time-to-silicon and reducing system integration risk.
The Arm SBSA Compliance Suite currently consists of 120 tests that can be run on a bare metal testbench generated by the Perspec System Verifier from a portable stimulus model of the design, offering compliance testing and faster debugging without involving the previously required Linux software stack. The reference example comes with a verification plan (vPlan) for the Cadence vManager Metric-Driven Signoff Platform, and the tests complete in minutes on the Palladium Z1 Enterprise Emulation Platform. A version of the reference example that is compatible with the Accellera Portable Test and Stimulus Standard (PSS) v1.0 will be available later in the fourth quarter of 2018.
Drew Henry, Senior Vice President and General Manager, Infrastructure Line of Business at Arm, stated: “The Arm SBSA Compliance Suite lets customers determine if an SoC is compliant with server requirements ahead of silicon, providing confidence that the design will function as intended. Through our continued collaboration with Cadence, we are enabling our mutual customers to use the Cadence tools and our SBSA Compliance Suite to create high-quality Arm-based server innovations more quickly with reduced risk.”
Paul Cunningham, Corporate Vice President and General Manager of the System & Verification Group at Cadence, added: “The complexity of thoroughly verifying hardware and hardware-dependent bare-metal software has been growing for years, and pre-silicon co-verification has become a must. Through our close collaboration with Arm and with the Palladium Z1 and Perspec technologies, we are making it easier for HPC customers to achieve better predictability with accelerated SoC delivery.”
The Palladium Z1 Enterprise Emulation Platform and the Perspec System Verifier are part of the broader Cadence Verification Suite. These tools support the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class JasperGold, Xcelium, Palladium Z1 and Protium S1 core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.