Synopsys announced that Renesas Technology Corp., the world's No. 1 supplier of microcontrollers and one of the world's leading semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets, has adopted Synopsys Proteus optical proximity correction (OPC) for 28-nanometer (nm) development. The 28-nm node pushes the limits for single-exposure photon-based lithography, and by selecting Proteus, Renesas can achieve ...

Synopsys introduced Design Compiler 2010, the latest RTL synthesis innovation within the Galaxy Implementation platform, which delivers a twofold speedup in the synthesis and physical implementation flow. To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimise iterations to speed up physical implementation. To address these challenges, topographical technology in Design...

Synopsys announced that it has enhanced its Galaxy Custom Designer solution with the addition of SmartDRD, an innovative design-rules-driven technology. SmartDRD technology enables layout engineers to more quickly achieve design-rule-check (DRC) clean designs with significantly reduced effort for analogue and custom designs. SmartDRD automates many DRC repair tasks, reducing hours of manual effort to mere seconds.

Synopsys and the Belgian nanoelectronics research center, imec, today announced they have entered into a collaboration to use Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools for characterising and optimising the reliability and electrical performance of through-silicon vias (TSVs). The collaboration will accelerate the development of 3D stacked IC technologies.

Synopsys announced that Yamaha, a leading provider of mobile audio and Graphics LSI chip products, achieved their aggressive performance targets ahead of schedule with Design Compiler(R) Graphical and successfully taped out their latest Graphics LSI chip.

Synopsys announced that APAC IC Layout Consultant, Inc., a global provider of IC physical design services, has adopted Synopsys’ Galaxy Custom Designer implementation solution. APAC IC, based in the Philippines, benefited from the ease with which Galaxy Custom Designer can be adopted to quickly achieve high productivity for its team of layout engineers servicing a worldwide customer base.

Synopsys announced that Aeroflex Colorado Springs, Inc., a global provider of high-technology solutions to the aerospace, defense and broadband communications markets, has successfully deployed Synopsys’ CustomSim unified circuit simulation solution for the development and verification of its high reliability integrated circuits (ICs). The CustomSim solution delivers performance improvements of up to 60x over SPICE, increasing designer producti...

Synopsys announced the addition of silicon-proven DesignWare MIPI IP consisting of 3G DigRF Controllers and PHY, Camera Serial Interface 2 (CSI-2) Host Controller and D-PHY to its IP portfolio. The Mobile Industry Processor Interface (MIPI) Alliance defines a set of standard hardware interfaces between mobile baseband processors, RF integrated circuits (ICs) and peripherals typically found in smartphones and multimedia handheld devices.

Synopsys announced the availability of high quality DesignWare High-Definition Multimedia Interface (HDMI) 1.4 transmitter (Tx) and receiver (Rx) digital controllers and PHY IP solutions that are compliant to the standard specification. With full support for new features of the HDMI 1.4 specification including HEAC, 3D formats, real-time content signaling, 4K x 2K resolution and 10.2 Gbps aggregate bandwidth, the DesignWare HDMI IP enables design...

Synopsys announced the DesignWare USB 3.0 Protocol Analyzer, a new graphical debugger for SuperSpeed USB 3.0, the latest generation of the USB interface that delivers 10 times the speed of Hi-Speed USB 2.0. The DesignWare USB 3.0 Protocol Analyzer simplifies debug for engineers verifying SuperSpeed USB 3.0 and USB 2.0 interfaces in their systems-on-chip (SoCs) by providing a graphical view of the protocol traffic. It helps users quickly identify...

Synopsys announced the availability of SuperSpeed USB 3.0 transaction-level models (TLM) supporting the Open SystemC Initiative (OSCI) TLM-2.0 API specification. The models are TLM representations of the Synopsys DesignWare(r) SuperSpeed USB 3.0 Device and xHCI Host Controller IP. The SuperSpeed USB 3.0 models enable pre-RTL and pre-silicon software development, verification and architecture exploration. They are part of the DesignWare System-Lev...

Synopsys announced the immediate availability of PrimeTime 2009.12, delivering up to 2X speed up of timing signoff through the addition of threaded multicore processing. With this latest addition, Synopsys’ PrimeTime tool provides a new level of flexibility enabling design teams to achieve optimal runtime performance across their heterogeneous multicore compute environments by utilising distributed and threaded multicore processing in tandem. ...

Synopsys today announced that X-FAB has expanded its support to include Synopsys’ Galaxy Custom Designer(TM) implementation solution. X-FAB now fully supports Synopsys’ Galaxy(TM) Implementation Platform across its wide range of advanced modular CMOS process technologies for analogue/mixed-signal (AMS) applications.

Tensilica has announced that it now provides out-of-the-box automated design flow support for key technologies within Synopsys' Galaxy Implementation Platform, including DC Ultra RTL synthesis and IC Compiler place-and-route, for Tensilica's new Xtensa 8 and Xtensa LX3 dataplane processors (DPUs). This latest design flow provides up to 15% improvement in processor speed, area and power, in addition to faster design closure over previous Synopsys-...

Synopsys, Inc. today announced that Loongson Technology Co., Ltd. achieved first-pass silicon success on its 65nm, multicore, high performance Loongson-3 CPU design using Synopsys’ CustomSim circuit simulator. The CustomSim solution was successfully deployed for timing and dynamic power simulation of advanced full-custom blocks, PLL, HyperTransport, register file, and content-addressable memory. The CustomSim solutions’s SPICE-level precisio...

Synopsys has announced that Hisilicon Technologies Co., Ltd., a worldwide provider of ASICs and solutions for communication network and digital media, and a subsidiary of Huawei Technologies, has established Synopsys as its primary EDA partner across its implementation and verification design flows. Hisilicon has signed an expanded business agreement to extend its use of Synopsys' IC Compiler place-and-route technology and DesignWare(R) IP as wel...

Synopsys, Inc. today announced the release of a broad range of data converter IP solutions for 40 nanometer (nm) process technologies. The IP is targeted at broadband wireless communications, wired communications and video designs requiring high-performance, ultra-low power consumption and very compact area. With this latest addition, Synopsys' DesignWare Data Converter IP portfolio now offers more than 100 data converter IP products comprised of...

Synopsys has announced that Realtek Semiconductor Corp, a leading provider of advanced IC products for communications network, computer peripheral and multimedia applications, has signed an expanded business agreement establishing Synopsys as its primary EDA partner. Under the new multi-year agreement, Realtek has extended its use of Synopsys’ Galaxy Implementation, Discovery Verification and Confirma Rapid Prototyping Platforms, as well as Syn...

Synopsys has announced that Arrow Electronics successfully deployed Synopsys’ TetraMAX automatic test pattern generation (ATPG) with multicore processing to significantly reduce the time needed to generate high quality manufacturing tests. Stringent quality goals combined with increasing design complexity stimulated the need to improve ATPG performance at Arrow. By utilising TetraMAX ATPG’s multicore processing capability on their quad-core ...

Synopsys has announced a new capability in DFTMAX compression that significantly reduces the cost of test for designs and methodologies that mandate very few test pins. Extending Synopsys’ patented adaptive scan technology with a high-performance, low-pin interface to the tester allows designers to achieve predictable compression of up to 100X or more with only one pair of test data pins. As designers must maintain test quality and reduce test ...