Imperas Software has confirmed the selection of the Imperas RISC-V reference model as part of their RISC-V processor verification work by Silicon Labs. RISC-V processor verification can be the most complex of tasks within an SoC verification plan and to address the flexibility and configurability of RISC-V it is important that the reference model supports user and privilege modes plus all the standard ratified RISC-V specification variant options...

Imperas Software has announced that the Free riscvOVPsimPlus RISC-V reference model and simulator, which has been widely adopted across the RISC-V ecosystem, has been updated and extended with additional features including full configurable instruction trace, GDB/Eclipse debug support, plus memory configuration options.

Imperas Software has been chosen by NSITEXE, a group company of the DENSO Corporation that develops and sells high-performance semiconductor IPs, for the development and verification of the next generation Automotive processor IP based on RISC-V with vector instruction extension.

Imperas Software has announced that OpenHW Group, the not-for-profit global organisation set up to facilitate collaboration between hardware and software designers in the development of open-source IP, has established the CORE-V processor verification test bench using the Imperas RISC-V reference model to deliver quality IP cores to the OpenHW Group ecosystem and the open source hardware community.

Imperas Software has announced that Mellanox Technologies has selected the Imperas advanced hardware verification of RISC-V processors.

Imperas Software has announced the certification of Coontec Design Center based in Pangyo Techno Valley, South Korea. The extensive partnership will provide customers with virtual platform design services to accelerate early stage software development and hardware verification schedules for SoC designs.