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Digital Core Design (DCD)

  • Wroclawska 94
    41-902 Bytom
    Poland
  • +48 32 282 82 66
  • http://www.dcd.pl
  • +48 32 282 74 37

Digital Core Design (DCD) Articles

Displaying 1 - 20 of 30
Analysis
6th December 2016
Embedded and scalable CPU named 'Product of the Future'

  The 'Polish Product of the Future' (Polski Produkt Przyszłosci - PPP) competition has been organised annually since 1997. Since 2008, the competition and promotion of winners has been co-financed by the European Union.

Displays
2nd November 2016
LCD display controller supports wide range of resolutions

An IP Core has been introduced by Digital Core Design - the DBLCD32 IP Core is a fully configurable, universal LCD/TFT display controller, which supports a range of resolutions. Moreover, it enables both, horizontal and vertical parameters’ synchronisation setup. The DBLCD32 IP Core is a fully configurable, universal LCD/TFT display controller.

Communications
17th October 2016
USB 2.0 device controller with ULPI Interface

  The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. DCD’s IP Core contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.

Communications
26th September 2016
Controller with flexible data-rate targets autonomous cars

Standalone controller for the Controller Area Network, (CAN), the DCAN FD is widely used in automotive and industrial applications. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (Flexible Data-rate) - in accordance to ISO 11898-1:2015.

Communications
14th July 2016
32-bit target interface meets PCI 3.0 requirements

The DTPCI32DC has been introduced to Digital Core Design's portfolio. It’s a Dual Clock 32-bit PCI Bus Target Interface IP Core which meets all requirements of the PCI 3.0 specification for a target device. Moreover, it compromises a minimal gate count with a high-bandwidth data transfer.

Events News
12th October 2015
Silicon solution boosts performance to 1.48/2.67DMIPS/MHz

Recognised as one of the most prestigious promotional events in the world, EXPO is a great opportunity to show the most innovative potential to a wider audience. Digital Core Design has been selected by the Ministry of Administration and Digitization (MAC) to present the D32PRO in a form of an interactive stand in the Polish pavilion from 12th to 18th October during Polish ICT Week at EXPO Milano 2015.

Communications
18th September 2015
32-bit CPU is fully scalable

  A fully scalable 32-bit CPU has been introduced by Digital Core Design. The D32PRO has been equipped with an FPU and a wide variety of available peripherals, including USB, Ethernet, I2C, SPI, UART, CAN, LIN, RTC, HDLC and Smart Card.

Design
11th May 2015
IP core is 75.08 times faster than predecessor

  Equipped with built-in on-chip debugger, the DQ80251 IP core has been introduced by Digital Core Design. The device executes MCS-51 and MCS-251 instruction sets 75.08 times faster than the company’s original 8051 core.

Design
31st March 2015
8051 MCU IP core is the industry's fastest

An 8051 MCU IP core, claimed to be the world’s fastest, has been introduced by DCD. Boasting a Dhrystone 2.1 performance rating of 0.27292 DMIPS/MHz, the DQ8051 IP core is 29.01 times faster than the original 80C51 chip operating at the same frequency. In addition, the IP core consumes as a little as 1.2µW/MHz. The closest competitor is 26 times faster than the original 80C51 chip and consumes almost two times more power than the DQ80...

Communications
12th March 2015
I2C core acts as master transmitter or master receiver

The I2C is a two-wire, bi-directional serial bus, which provides simple and efficient method of short distance data transmission between many devices. But reality shows that the I2C bus can be very confusing, not just for newcomers. The DI2CM core from Digital Core Design, of Poland, provides an interface between a MPU or MCU and the I2C bus. It can work as a master transmitter or a master receiver.

Design
3rd February 2015
Platform enhances USB HID design

A platform, developed to enhance USB HID design, has been introduced by Digital Core Design (DCD). The design platform addresses the challenge of a true programmable embedded SoC integrating configurable analogue and digital peripheral functions. 

Communications
3rd December 2014
MCU core features sophisticated on-chip peripherals

Digital Core Design has introduced the D6811E IP Core, a redefined 8-bit MCU IP Core with highly sophisticated, on-chip peripheral capabilities, aimed at IoT sensors and beacons. Thanks to its binary compatibility with Motorola’s 68HC11 MCU, the core can be implemented in barcode readers, hotel card key writers, robotics, and various embedded systems.

Design
7th November 2014
Instruction Smart Trace aids transparent SoC debugging

  Digital Core Design has enhanced its 8051 portfolio with the functionality of an Instruction Smart Trace. The DP8051, DP80390, and DQ8051, thanks to an Instruction Smart Trace (IST), can all efficiently reduce trace memory size and increase traced programme history.

Design
3rd October 2014
D68HC11K with applications notes, development board & tools from Digital Core Design

In a standard configuration, the core has an integrated on-chip major peripheral functions. An asynchronous serial communication interface (SCI) and a separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. 

Communications
20th June 2014
IP Core performs a serial-to-parallel conversion

DCD’s UART IP Core performs a serial-to-parallel conversion on data characters received from a peripheral device or a MODEM. And for those who need more, the D16950 enables also parallel-to-serial conversion on data characters received from the CPU. The processor can read a complete status of the UART at any time during the functional operation.

Design
5th February 2014
IP Core exchanges data between EEPROM and CPU’s RAM

Targeted specifically for DRAM designs, Digital Core Design has introduced the DEEPROM IP Core. Suitable for applications requiring data storage in external non-volatile memories, the DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface.

Communications
9th January 2014
IP core combines reduced CPU utilisation & low area consumption

Designed for smart reader applications, the DSMART is an IP core combining highly reduced CPU utilization & low area consumption. The DCD IP core is also designed to be able to activate and deactivate cards, perform resets, handle ATR reception, as well as other additional features.

FPGAs
2nd December 2013
DCD’s HDLC/SDLC controller aims telecommunication

The latest latest soft IP Core, the DHDLC, has been announced by Digital Core Design. Designed to control HDLC/SDLC transmission frame and optimized for great variety of 8, 16 and 32-bit MCUs, the DHDLC is a technology independent design and can therefore can be implemented in both ASIC and FPGA.

Communications
4th November 2013
Soft core of programmable interrupt controller

DCD have today introduced the D8259, a soft core of programmable interrupt controller. Fully compatible with the 82C59A device, DCD’s IP core can manage up to 8-vectored priority interrupts for the processor. The D8259 can also be programmed to cascade and gain up to 64 vectored interrupts. Programming the D8259 to the Poll Command Mode, users can get more than 64 vectored interrupts.

Design
8th October 2013
DSPI_FIFO – SPI master slave enhanced with detectors

Digital Core Design has presented the newest SPI IP Core enhanced with useful design features. The DSPI_FIFO is a fully configurable SPI master/slave device, which allows to configure polarity and phase of a serial clock signal SCK. DCD’s core enables microcontroller to communicate with serial peripheral devices, but also to communicate with an interprocessor in a multi-master system. It supports all the features of SPI and transmission/rec...

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