Cadence Design Systems
Cadence Design Systems Articles
Cadence OrCAD PSpice Technology to be Used by STMicroelectronics to Help its Customers Evaluate Analog and Power ICs
Cadence Design Systems, Inc. today announced that STMicroelectronics has selected Cadence OrCAD PSpice technology to provide simulation capabilities to its customers to evaluate the company’s analog and power IC’s.
CDNLive! EMEA Invites Cadence Customers to Go “Beyond Imagination”
Cadence Design Systems, Inc. inaugurates its 2010 series of worldwide technical conferences with CDNLive! EMEA (Europe, Middle East and Africa) taking place in Munich, Germany, from May 4 to May 6. It is the first of six worldwide user conferences to be held this year, followed by events in Japan, China, North America, Israel, and India. CDNLive! EMEA brings together hundreds of Cadence® technology users, developers and industry experts to excha...
ChipEstimate.com Announces New IP Partners
ChipEstimate.com announced today that more than two dozen IP companies recently have joined or upgraded their memberships to the ChipEstimate.com chip planning and IP portal. New members joining at the Prime Plus partner level include True Circuits, Inc., Virage Logic and Xilinx. New members joining at the Prime partner level are Alvand Technologies, Boeing, ChipStart, Evatronix, HDL Design House, Imagination Technologies, National Semiconductor...
Energy Micro Uses Cadence Low-Power Solution to Develop its Latest Energy-Efficient Microcontroller
Cadence Design Systems today announced that Energy Micro, the energy friendly microcontroller company, deployed Cadence Low-Power Solution, to develop a highly power efficient ARM Cortex M3-based microcontroller that significantly saves battery life.
Cadence Europe Expands Its Academic Network
Cadence Design Systems announced that three additional universities will take on active roles in its academic network in Europe. The network promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. The latest additions to the Cadence Academic Network are the CETTI/TU Bucharest, which will focus on PCB design; the KTH Stockholm, which will concentrate on wireles...
Chipsbank Adopts Cadence Incisive Xtreme III System to Boost SoC Verification Performance
Cadence Design Systems announced that Chipsbank Microelectronics Co., Ltd., a leading fabless IC design company based in Shenzhen, China, has adopted the Cadence Incisive Xtreme III system to accelerate the RTL design process with a verification flow for its next-generation digital consumer and networking chips.
Cadence Encounter Digital Implementation System 9.1 Addresses Industry Productivity Crisis for Complex System-on-Chip Design
Cadence Design Systems has released Cadence Encounter Digital Implementation (EDI) System 9.1, a complete and integrated digital design, implementation, and verification environment for the development of large-scale, complex SoCs. The new and expanded suite of capabilities in EDI System 9.1 answers the industry call for improved designer productivity in developing advanced low power and mixed signal SoCs at leading-edge process nodes – such as...
Cosmic Circuits Adopts Cadence Virtuoso 6.1 for Complex Analog and Mixed-Signal Designs
Cadence Design Systems (I) Pvt Ltd., a subsidiary of Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Cosmic Circuits, a leading provider of differentiated analog IP cores, has adopted the Cadence® Virtuoso® IC 6.1 custom design platform. After extensive and rigorous testing, Cosmic selected Virtuoso IC 6.1 for its complex analog and mixed-signal layout flow, and immediately ga...
Zoran Deploys Cadence Virtuoso Software for Complex, Advanced Technology, Mixed-Signal Chip
Cadence Design Systems today announced that Zoran Corp., a leading provider of digital solutions in the digital entertainment and imaging markets, taped out a complex, advanced technology mixed-signal chip using the Cadence® Virtuoso® suite of design and simulation products. Zoran adopted the Virtuoso technology to address the growing complexities and challenges its engineers faced moving to advanced nodes.
Fairchild Semiconductor Selects Cadence as Primary EDA Partner
Cadence has announced that Fairchild Semiconductor, a leading global provider of energy-efficient semiconductor technology, has named Cadence as its primary EDA partner following the signing of a multi-year agreement for key Cadence mixed-signal technology.
AppliedMicro Standardizes on Cadence Encounter Digital Implementation System
Cadence Design Systems today announced that Applied Micro Circuits Corporation has selected the Cadence Encounter Digital Implementation (EDI) System for its large, complex advanced-node designs. EDI System joins other multiprocessing-capable offerings in the AppliedMicro methodology to form a standardized design infrastructure based set of tools.
AppliedMicro Standardizes on Cadence Encounter Digital Implementation System
Cadence Design Systems today announced that Applied Micro Circuits Corporation has selected the Cadence® Encounter® Digital Implementation (EDI) System for its large, complex advanced-node designs. EDI System joins other multiprocessing-capable offerings in the AppliedMicro™ methodology to form a standardized design infrastructure based set of tools.
Cadence Strengthens Virtuoso Custom IC Design Leadership
Cadence Design Systems today extended its leadership position in analog and mixed-signal chip design technologies with the introduction of dramatic improvements to its leading Virtuoso IC design platform. Cadence announced powerful performance, capacity and usability enhancements in Virtuoso IC6.1.4 that reduce overall design time while ensuring high-quality production ICs.
IC Plus Standardizes Verification Process with Cadence Incisive Solution
Cadence Design Systems today announced that IC Plus, a communication and networking IC design company in Taiwan, has adopted the Cadence Incisive verification solution with the Open Verification Methodology (OVM) and Cadence verification IP (VIP) to optimize development time while simplifying and standardizing its verification process.
Exar Selects Cadence as Mixed-Signal EDA Provider
Cadence Design Systems announced today that Exar Corporation has signed an expanded business agreement to establish Cadence® as its leading chip planning and mixed-signal design solutions provider. As a result of the new multi-year agreement, the Cadence Virtuoso® and Encounter® platforms, as well as the Cadence Chip Planning Solution, will make up Exar's key mixed-signal design environment for designs at 65 nanometers and below.
Cadence Marks Annual Innovation Day with Honors for its Top Technology Leaders
Cadence Design Systems today is celebrating Innovation Day, honoring the contributions Cadence employees have made to the company and the electronics industry as a whole. Having garnered more than 800 U.S. patents and an additional 150 international patents, Cadence has a long legacy of technology innovation that has enabled EDA customers to successfully create some of the world’s most recognized consumer and business products for over 20 years...
Silicon Hive Utilizes Cadence Palladium III Solution for Highest Quality IP for Multi-Core Multi-Million Gate Designs
Cadence Design Systems has announced that Silicon Hive, a worldwide supplier of semiconductor intellectual property (IP), achieved the highest quality for its HiveGo mobile imaging and video decoding solutions using the Cadence Palladium III Accelerator/Emulator. Palladium technology enabled Silicon Hive to meet aggressive IP quality requirements for multi-core, multi-million-gate designs targeting mass-market consumer products.
Cadence Reports Q3 2009 Financial Results
Cadence reported third quarter 2009 revenue of $216 million, compared to revenue of $232 million reported for the same period in 2008. On a GAAP basis, Cadence recognized a net loss of $14 million, or $(0.05) per share on a diluted basis, in the third quarter of 2009, compared to a net loss of $171 million, or $(0.67) per share on a diluted basis in the same period in 2008.
SMIC and Cadence Announce 65-Nanometer Low power Reference Flow 4.0
Cadence Design Systems has announced that it has delivered a comprehensive low-power design flow for engineers targeting the 65-nanometer process at Semiconductor Manufacturing International Corporation . Based on the Cadence Low-Power Solution, the flow enables faster design of leading-edge, low-power semiconductors using a single, comprehensive design platform.