Cadence Design Systems
- Bagshot Road
Bracknell
Berkshire
RG12 OPH
United Kingdom - +44.1344.360333
- http://www.cadence.com
- + 44.1344.869647
Cadence Design Systems Articles
Cadence Executives Offer Insight on Memory Trends Impacting Cloud Computing and Mobility
Cadence has announced that it will showcase the company’s expertise in memory design IP at MemCon 2012. Martin Lund, senior vice president of research and development, SoC Realization Group at Cadence, kicks off MemCon 2012 with his keynote speech, “How Cloud and Mobility are Disrupting the Memory Ecosystem” on Tuesday, September 18, from 9:30-10:00 AM.
Cadence Announces Industry’s First DDR4 Design IP Solutions Are Now Proven in 28nm Silicon
Cadence Design Systems today announced that the first products in the Cadence DDR4 SDRAM PHY and memory controller design intellectual property family have been proven in silicon on TSMC’s 28HPM and 28HP process technologies.
Denso Gains Significant Productivity and Quality-of-Results Advantages with Cadence Mixed-Signal, Low-Power Solutions
Cadence Design Systems, Inc announced today that automotive parts manufacturer Denso Corp. experienced significant quality and productivity improvements on a low-power mixed-signal IC design after switching to Cadence custom/analog and digital flows. After deploying the Cadence Encounter RTL-to-GDSII flow on the digital portion of the design, Denso reported a 10 percent reduction in area and a 20 percent reduction in power compared to previous ve...
Cadence and MIET Celebrate 10 Years of a Successful Master’s Degree Program
Cadence and the National Research University of Electronic Technology (MIET) today announced the 10th anniversary of a graduate program in analogue and mixed-signal design for Russian engineering graduate students seeking a master’s degree in electrical engineering.
Cadence Thesis Contest for Automotive Embedded Systems
Cadence Design Systems announced the launch of a thesis contest for automotive embedded systems. The objective of the contest is to attract submissions of Diploma, Bachelor, and Master theses about best methodologies, flows, designs and tools for automotive embedded systems designs based on SystemC.
Cadence Encounter Digital Technology Helps Renesas Gain Advantage in Design Power, Area and Productivity
Cadence Design Systems, Inc announced today that Renesas Electronics Corporation, significantly improved power, area and productivity by using Cadence Encounter digital technology to tape out its new generation of automotive 32-bit microcontrollers (MCU). These latest MCUs were designed specifically for integrating system control and network processing functions of car infotainment devices on one chip.
Cadence Announces Q2 2012 Financial Results
Cadence have today reported financial results for the second quarter of the 2012 fiscal year. Cadence reported second quarter 2012 revenue of $326 million, compared to revenue of $283 million reported for the same period in 2011. On a GAAP basis, Cadence recognized net income of $36 million, or $0.13 per share on a diluted basis in the second quarter of 2012, compared to net income of $27 million, or $0.10 per share on a diluted basis in the same...
PCI Express Verification IP from Cadence Receives PIPE4 suuport
Cadence have today revealed powerful new capabilities added to its PCI Express Verification IP which allow more in-depth verification of the most current PCI Express specification at both the block and system-on-chip levels.
Cadence Acquires Sigrity
Cadence Design Systems, Inc. has announced it has acquired Sigrity, Inc. Sigrity provides a rich set of gigabit signal and power network analysis technologies, including a unique power-aware signal integrity analysis capability for system, printed circuit board, and IC package designs.
Cadence Encounter Digital Technology Provides Ambarella With Big Improvements in Power, Performance and Area
Cadence Design Systems, Inc announced today that Ambarella realized significant improvements in power, performance and area on a recent 32-nanometer gigahertz SoC design by upgrading to the latest Cadence Encounter RTL-to-GDSII flow.
Cadence Physical Verification System Qualified for TSMC 28nm, 20nm Process
Cadence Design Systems, Inc. today announced that TSMC has qualified the Cadence Physical Verification System for 28-nanometer design signoff, and completed Phase I certification for TSMC’s 20-nanometer process. Designers can request a PVS 20-nanometer technology file directly from TSMC for early design exploration, and access TSMC-Online to download 28-nanometer technology files for signoff.
Cadence Encounter and Virtuoso Design Platforms Receive TSMC 20nm Phase I Certification
Cadence Design Systems, Inc. today announced that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff. TSMC certified the tools for 20-nanometer design rule manuals and SPICE models.
Cadence Collaborates on 3D-IC Design Infrastructure with TSMC
Cadence Design Systems, Inc. today announced its collaboration with TSMC on 3D-IC design infrastructure development. 3D-ICs require co-design, analysis and verification of heterogeneous chips and silicon carriers. Coming from multiple disciplines and product areas, TSMC and Cadence teams worked together to create and integrate features to support this new type of design, culminating in the test-chip tapeout of TSMC’s first heterogeneous CoWoS v...
Samsung and Cadence Deliver 20nm Digital Design Methodology
Cadence Design Systems, Inc. today announced that Samsung Electronics and Cadence have collaborated to deliver a 20-nanometer design methodology that incorporates double patterning technology for joint customer deployment and internal test chips. The collaboration between Cadence and Samsung brings new process advances for mobile consumer electronics, enabling design at 20 nanometers and future process nodes.
Cadence Announces Updated Design and Verification IP for DDR PHY Interface
Cadence Design Systems, Inc. today announced that the company’s comprehensive suite of DDR controller and DDR PHY design IP as well as its Cadence Verification IP Catalog now support the latest release of the DFI specification, version 3.1. The new version adds support for the LPDDR3 mobile memory standard for smartphones and tablets, and includes enhancements to the PHY’s low-power interface and training features.
Nufront's Third-Generation Mobile Applications Processor Powered by Cadence DDR3/3L/LPDDR2 Memory Interface IP Solution
Cadence Design Systems, Inc. today announced that Nufront’s NS115 chipset integrated the Cadence configurable DDR3/3L/LPDDR2 Memory Controller and Hard PHY IP core in its dual-core ARM Cortex-A9 based mobile applications processor. The TSMC 40nm LP 32-bit DDR3/3L/LPDDR2 interface features a data rate of up to 800Mbps while providing the automated traffic-based power management and efficiency critical to the ultrabook, tablet and smartphone mark...
Cadence Introduces New NVM Express IP Solutions for Solid State Storage Applications
Cadence Design Systems, Inc. today launched the industry’s first IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard, an interface technology used in the rapidly growing solid-state drive market. The solution includes Cadence Design IP for NVM Express controller and Cadence Design IP for NVM Express subsystem.
Cadence Expands System and SoC Verification Offerings to Accelerate System Integration and Reduce Time to Market
Cadence Design Systems, Inc. continued its efforts to help customers reduce time to market for new systems and SoCs with the announcement of new in-circuit acceleration based on the Incisive and Palladium XP platforms for the company’s System Development Suite, and extensions to the Verification IP Catalog for acceleration and emulation to give engineers the ability to go beyond simulation to speed verification of large-scale SoCs, sub-systems ...
Fujitsu Semiconductor Adopts Cadence Chip Planning System for MCU Chips at Its Design Centers Worldwide
Cadence Design Systems, Inc. today announced that Fujitsu Semiconductor Limited has adopted the newly updated Cadence Chip Planning System at its nine design centers spread around the globe. Fujitsu Semiconductor chose the Cadence system because of the time, accuracy and cost benefits it offers in the development of its MCU chips requiring large-scale integration (LSI).
Cadence OrCAD Capture Marketplace Now Available on Desktop Browsers
Cadence Design Systems, Inc. announced the availability of its ground-breaking Cadence OrCAD Capture Marketplace to the entire OrCAD and Allegro PCB design community through a standard desktop browser, as well as the addition of several new apps and a trial period for paid apps.