ASSET InterTech has published a new eBook on how to test DDR memory with non-intrusive JTAG or boundary-scan (IEEE 1149.1) methods. A recent survey of engineers by the International Electronics Manufacturing Initiative (iNEMI) found that testing memory soldered to circuit boards is a major problem for system manufacturers.

Asset InterTech can now cover the entire debug to production test cycle on systems on a chip (SoCs) and circuit boards with the acquisition of Arium. The deal will see Arium’s software debug and trace capabilities integrated onto Asset InterTech’s ScanWorks platform by the end of this year.

ASSET InterTech have today announced the introduction of a new eBook that will help circuit board manufacturers who want to recover their investment in assembled boards that won’t boot – so called dead boards – and still maintain the tight production deadlines that constantly reduce the time they can spend on board debug.

A new eBook from ASSET InterTech explains how the structural test methodology based on the IEEE 1149.1 boundary scan standard, known as JTAG, can apply functional tests to I2C and SPI system monitors during prototype board bring-up and later during production of the circuit board.

With the new PXI-based controller for ASSET InterTech’s ScanWorks platform for debug, validation and test, engineers can test circuit boards with four different toolsets, each based on a different test technology.

A new e-book from ASSET InterTech, Cache-as-RAM for board bring-up of non-booting circuit boards, takes a close look at how run-control tools can employ a processor’s on-chip cache memory instead of on-board RAM memory to boot non-booting prototype circuit boards.

A new white paper from ASSET InterTech explains why test coverage from intrusive, probe-based in-circuit testers with their bed-of-nails fixtures is diminishing. The paper also describes software-based non-intrusive methodologies that test from the inside out and eliminate the need to physically probe chips and circuit boards during prototype board bring-up, volume manufacturing and troubleshooting in the field.

A new white paper from ASSET InterTech points out how increasing bus speeds on circuit boards could create havoc for signal integrity on those buses, in turn degrading the bus’ throughput performance. Each new generation of a high-speed bus typically runs at a higher signal frequency, but this decreases the margin for error on the bus, making it more sensitive to disruptions from jitter, inter-symbol interference, crosstalk and other factors.

ASSET InterTech and Teradyne have extended the integration of the JTAG and boundary-scan test capabilities of ASSET's ScanWorks platform for embedded instruments into Teradyne's PXI Express-based High Speed Subsystem.

Designers of micro server circuit boards based on the Intel Atom processor now have for the first time a tool capable of non-intrusively validating the signal integrity on high-speed input/output and memory buses. The ScanWorks platform for embedded instruments from ASSET InterTech is the first design validation tool for Intel Atom designs that does not rely on placing a physical probe on a bus to monitor its signal integrity.

ASSET InterTech has today announced an addition of two new memory test instruments to its ScanWorks embedded instrumentation library for its FPGA-controlled test circuit board test tool, giving electronics manufacturers a cost-effective non-intrusive means of increasing test coverage.

A new white paper from ASSET InterTech explains how non-intrusive software-driven embedded instruments can overcome many of the challenges of testing, validating and debugging high-speed memory buses such the DDR 3 or DDR4 (DDR3/4) buses, and others.

Two new controller kits for the ScanWorks platform for embedded instruments from ASSET InterTech can accelerate test throughput by plugging into the high-speed PCI Express bus in the personal computer where ScanWorks is running. The new controller kits can apply ScanWorks non-intrusive board tests to a circuit board.

With new tools for the ASSET ScanWorks platform for embedded instruments, design engineers can for the first time structurally verify, functionally test, analyze performance margins and debug boards based on the Intel microarchitecture codenamed Haswell within one unified software environment. This accelerates the new product introduction cycle by providing a single user interface for correlating the root causes of design issues.

Bringing up prototype circuit boards is a tipping point in the product development cycle. Unfortunately, it too often becomes a tripping point. Boards that won’t come up can derail the project entirely, delaying the launch of the product into the market and generating staggering opportunity costs. Board bring-up must verify the functionality of the hardware so that application software can be loaded and debugged. Without a known-good-board, dia...

The new Remote Instrumentation Controller 4000 (RIC-4000) for ASSET's ScanWorks platform for embedded instruments can connect over an Ethernet network and apply boundary scan (JTAG) tests on as many as four circuit boards at once. The units under test (UUT) and ScanWorks could be in the same room on the same local network or they might be across the globe, connected over the Internet.

With new tools for the ASSET ScanWorks platform for embedded instruments engineers can simply select instruments they need, set their parameters and insert them into a field programmable gate array to function as a circuit board tester. Once inserted, ScanWorks FCT operates the board-tester-in-a-chip from a drag-and-drop user interface to perform validation, test and debug.

When circuit board designs for desktop and mobile applications roll out with Intel® CoreT processors based on the new Intel microarchitecture codenamed Haswell, ASSET®'s ScanWorks® platform for embedded instrumentation will be the only tool able to access Intel's embedded instruments and perform advanced validation on all of a board's high-speed buses.

A new model-based test methodology for ASSET® InterTech's ScanWorks® platform for embedded instruments extends non-intrusive boundary-scan (JTAG) test coverage to devices that previously could not be tested or programmed with boundary scan. ASSET is the leading supplier of tools for embedded instrumentation.

ASSET InterTech has joined the PCI-SIG® and plans to participate in the group's upcoming interoperability workshops. As a result, manufacturers of PCI Express (PCIe) add-in cards (AIC) will be able to validate that their cards interoperate with ASSET's ScanWorks platform for embedded instruments. This ensures that the AIC manufacturer can access Intel®'s embedded instrumentation technology, Interconnect Built-In Self Test (IBIST), because ScanW...