HDL Design House Announces PCS IP Core

The PCS is responsible for generation of idle characters, lane striping and encoding on transmission and decoding, lane alignment and restriping on reception. The PCS uses an 8B/10B encoding for transmission over the link. The PCS IP Core provides two kinds of loopback capabilities, the external one that comprises 8B10B encoders/decoders only and internal that comprises both 8B10B encoders/decoders and super-frame generation/recovery.

For test purposes, the PCS IP offers built-in PRBS generator/verifier pairs. The PRBS pairs are implemented in two levels, the super-frame level and per-lane level.