ZESTRON to Present PoP Cleaning Study at the SMTA China East Conference in Shanghai

Package on package (PoP) assemblies are widely growing in use for applications that require small footprint technology. Typically, this integrated circuit design stacks and integrates logic and memory packages, thereby increasing board density and substantially expanding functionality within the same footprint of a single BGA. As a result, PoP’s have become an ideal component selection for products such as advanced mobile platforms and digital cameras.

This technical paper, presented by Mr. Jerry Ji, will emphasize how effective cleaning improves product reliability by ensuring optimal surface resistance between the solder bumps and by preventing current leakage that can lead to PCB failure. Furthermore, this technical paper will address the cleanliness level of required PoP assemblies including underneath PoP components and in between packages. Expected results will empirically confirm the effectiveness of cleaning technologies for this rapidly evolving technology.