ilica's customers have used the company's customizable dataplane processor (DPU) technology to design their own digital signal processors (DSPs) for the past 10 years. Two years ago, Tensilica formed its baseband business unit and has since enjoyed great success as the rising star in programmable baseband signal processing. Customers include Fujitsu, Huawei, NEC, Panasonic, and many other major undisclosed companies, all of whom are engaged in LTE (Long-Term Evolution) and 4G baseband chip design with Tensilica's DPUs and ConnX(TM) baseband DSPs. Tensilica's DPUs and ConnX baseband DSPs are ideal for baseband because they can be customized to provide greater power and performance efficiency than standard DSPs.
Because of our solid DPU foundation and success in baseband signal processing, we've been able to ramp up quickly and add top engineering talent to our team, stated Jack Guedj, Tensilica's president and CEO. Now, with Eric, we're reaching critical mass with strong leadership to help us continue our growth trajectory.
It's exciting to join an aggressive company that's rapidly becoming the architecture of choice for programmable baseband signal processing, Dewannain stated. The amazing thing is how fast we can develop new products and provide optimized solutions for the mobile wireless market using the same Xtensa(TM) DPU foundation and tools we license to our customers. Leveraging this strong Xtensa DPU foundation, Tensilica has been able to develop a comprehensive IP (intellectual property) suite tailored for LTE and introduce two generations of ConnX BBE baseband DSPs in less than two years. Any other IP vendor would take several years to develop these products.
Dewannain spent the last 18 years at TI, most recently as general manager of TI's custom ASIC business unit. He also served as the general manager of the communications infrastructure ASIC business unit, and general manager of the cable broadband communications business unit. Prior to TI, he worked as a circuit design manager on the Pentium design team and a senior design engineer on the 80486 design team at Intel. He has an M.B.A from the University of Phoenix and an M.S.E. E. from the Institut Superieur D'Electronique in France.