STI Electronics’ Casey Cooper to Discuss SIR Test Protocols at the 2011 Pan Pacific Microelectronics Symposium

High-reliability electronics pose a higher risk of failure when operating in harsh environments such as high-temperature and high-humidity. Add the possibility of ionic contaminants left on the substrate surface from the electronics manufacturing processes and the result is a situation set for failure. One common test standard used to evaluate the effects of assembly materials and manufacturing processes (i.e. residual materials) for hardware operating in hot, humid environments is the Surface Insulation Resistance (SIR) test.

This paper will study a customized test protocol designed to environmentally stress screen conformal coatings for their ability to withstand moisture ingression and protect the conductors from moisture-related failures such as corrosion and dendritic growth formations. The analysis of data captured from continuous voltage monitoring (for dendritic growth/shorts) in addition to traditional SIR testing will provide the manufacturing engineer with the necessary data to evaluate and identify the optimal material set and process parameters to manufacture high-reliability electronics for operation in harsh environments.

Casey is involved with the development of Imbedded Component/Die Technology (IC/DT®) at STI and its implementation into military, aerospace and commercial applications. Mrs. Cooper has more than nine years of experience with microelectronics packaging beginning with her involvement at the Center for Advanced Vehicle Electronics (CAVE) as a co-op student while studying Electrical Engineering at Auburn University. She also served as an intern for the Microelectronics Technology group at Harris Corporation in Melbourne, FL, where she was involved with the redesign of a multichip module LTCC layout.