JTAG Technologies To Showcase Latest Product Developments at Autotestcon 2012

3rd September 2012
Posted By : ES Admin
JTAG Technologies To Showcase Latest Product Developments at Autotestcon 2012
JTAG Technologies will be showcasing latest developments and products at Autotestcon Anaheim in September this year. Amongst our variety of military and aerospace products, these latest models deserve attention and will be presented at Autotestcon.
New JTAG Boundary Scan Tester/Programmer – Partnership with Astronics Corp
The JTS1000 is a Universal JTAG Boundary Scan Tester and Programmer that can be utilized as a Production Run Time and Application Development system for performing Circuit Card Assembly structural integrity tests or CCA programming. The available assets packaged within a small footprint make the JTS1000 suitable for both Production and Field Testing. The JTS1000 utilizes Astronics DME's Test EZ Software Suite for automated testing and program development.

Other standard features include:

• Standalone bench-top LXI-based system
• JTAG TAPS with up to 256 programmable digital I/O channels
• 6.5 digit DMM
• Power and multiplexed switching
• 16 port Ethernet switch
• Up to 4 programmable DC power supplies
• Plus various software
Our partner Astronics Corporation is a leader in advanced, high performance lighting, electrical power and automated test systems for the global aerospace and defense industries. Astronics Corporation, and its wholly-owned subsidiaries Astronics Advanced Electronic Systems Corp. Astronics Luminescent Systems Inc. and Astronics DME have a reputation for high quality designs, exceptional responsiveness, strong brand recognition and best-in-class manufacturing practices.

JFT by JTAG Technologies
JTAG Technologies recently introduced high-level JTAG access routines, which can be linked into the Python™ freeware open-source language. Called JTAG Functional Test routines, they work at two levels (or perspectives), namely: boundary-scan pin-level and ‘cluster’ pin-level.
In the boundary-scan pin-level example users can set-up tests with minimal knowledge of the interconnections and without reference to a design netlist. Individual pins can be driven using DriveHigh, DriveLow and HighZ and individual pins can be read using TestHigh and TestLow .
Also, groups of pins can be defined by DeclareGroup. For example, the pins of a JTAG-compliant device which connect to a (non-JTAG-compliant) DAC might be grouped and named ‘DAC-input’. The variable ‘DAC-input’ can then be controlled using a DriveVar command. Similarly, the output of an ADC could be suitably-named and read by a TestVar routine.

Easy to use for Design Engineers
Using JFT at this level allows design engineers to undertake debug sessions without the need to create specific test firmware or FPGA test configurations. Equally, repair or service personnel can easily create test scripts to cover well-known fault signatures. The cluster pin-level perspective takes testing to the next level/stage by allowing the user to specify pin-level and variable-level drives - testing from the device under test’s point of view.

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