IP offers seamless integration of USB 2.0 functionality into advanced SoCs from 40nm

The PHY provides all of the functionality needed to process the USB protocol and the physical layer signalling for USB 2.0 Hi-Speed (HS) 480Mbps operation as well as USB 1.1 Full-Speed (FS) transmission at 12Mbps and Low-Speed (LS) transmission at 1.5Mbps. SYNC detection, parallel-to-serial and serial-to-parallel data conversion, and data recovery are all supported.

Toshiba’s IP comprises a transceiver module, a common PLL/bias block, digital control logic, and ‘On-the-Go’ (OTG) functionality. The common block includes an internal clock generator for accurate HS data transmission. The integrated PLL can operate either from an external crystal or an internal clock source. All required reference currents and voltages are generated in this block. USB 2.0 compliant serial data transmission is provided by the transceiver module, which handles transmission and reception including data recovery for HS, FS and LS signalling. Data processing including serializer/deserializer bit stuffing is performed in the digital control block. This block supports ATE and provides a UTMI+L3 compliant interface. The OTG block contains the prerequisites for realizing the USB-OTG functionality that allows for PC-less communication between products.

Fully silicon-proven, Toshiba’s USB 2.0 PHY is available for seamless integration into the company’s TC340 40nm 1.0V, TC320 65nm 1.2V and TC300 90nm 1.2V processes and, without OTG functionality, its TC280 130nm 1.5V process. The block is supplied as a mixed-signal hard macro and GDSII, abstracts, models for major EDA tools and detailed application notes can all be supplied. In addition, designers at Toshiba’s European LSI Design and Engineering Center (ELDEC) are available to provide full technical support, advice and guidance relating to the deployment of SoCs incorporating USB functionality.