Imec, Coventor partner to drive advanced CMOS process

To adopt the 7nm node, the industry needs to select the optimal layout, as well as optimize process step performance and control methodology.

Using Coventor’s SEMulator3D platform, engineers from imec and Coventor are working together to reduce silicon learning cycles and development costs by down selecting the options for development of next-generation manufacturing technologies.

The SEMulator3D platform is an integrated set of modelling tools with enhanced visibility, accuracy and performance that enables engineers to interactively model and simulate a wide range of manufacturing effects in software before committing to expensive test chips.

At imec, process and integration experts have connected optical lithography simulations with Coventor’s SEMulator3D virtual fabrication platform to explore FinFET scaling to the 7nm node and to compare the process window marginalities in several dense SRAM designs using Spacer Assisted Quadruple Patterning and either multiple immersion or EUV patterning cut/keep solutions. Moreover, a Spacer-Assisted Quad Patterning scheme for 7nm dense interconnect was devised using SEMulator3D, and process window marginalities for an immersion based multiple block patterning solution were analysed. Additional collaboration will focus on the predictive modelling of Directed Self-Assembly for advanced patterning.

An Steegen, senior vice president process technology at imec said: “A virtual fabrication platform enables us to tie together integrated processing before all of the individual processes are available. The SEMulator3D tool gives us the visibility and accuracy to do that, and an integrated platform to bring together all the various elements of advanced processing before moving on to actual silicon.”

“Imec is the premier semiconductor research center, and this collaboration allows us to synchronize our modelling roadmap with one of the industry’s most advanced process roadmaps, as well as to speed the development of their 10nm and 7nm technology,” said David Fried, Chief Technical Officer, Semiconductor, at Coventor. “Working together with imec on novel integration schemes, designing SEMulator3D-specific structures for imec’s test sites, and then calibrating advanced models to imec’s wafer processing is an extremely effective and valuable way for Coventor to optimize our virtual fabrication platform for emerging market requirements.”