Evaluation board taps potential of Tester on Chip

As a result, the entire range of performance of the CION LX chips and the potential of the Embedded System Access (ESA) technology can be achieved.

The pins of the circuit are accessible via connectors. The board also provides additional resources such as LEDs and an adjustable clock generator up to 170MHz, which is an ideal base for tracking frequency measurements or signal recordings by the digital Waveform recorder.

Control of the features is carried out thropugh the JTAG port. In addition, the Evaluation Board has a TAP connector which allows direct access via Boundary Scan controllers such as the PicoTAP.    

The CION LX was developed in 0.35 µm mixed-signal CMOS technology and provides four independent I/O ports. Each port can be individually operated in a voltage range from 0.9 V to 3.6 V. The integrated Boundary Scan architecture supports the standards IEEE 1149.1, IEEE 1149.6 and IEEE 1149.8.1, at a maximum TCK frequency of 100 MHz. In addition to the single-ended pins, the CION LX provides differential signals as well as interfaces with increased driver capability. Four operation modes enable the IC‘s flexible utilisation as a purely serially controlled JTAG transceiver, parallel I/O buffer, latched bus transceiver, and pin driver.

Additionally, instruments such as digitiser, arbitrary waveform generator, event counter, frequency meter and toggle detectors are integrated into the CION LX. These instruments can be accessed – depending on operation mode – either serially via the JTAG Test Access Port (TAP) or a parallel control bus. The instruments can be activated simultaneously to Boundary Scan operations and per test channel. For each channel, pull-up and pull-down resistors can also be connected and the drivers‘ slew rates can be programmed.