GOEPEL electronic enlists chip-embedded instrumentation for high-speed RAM Access Test

26th September 2011
Posted By : ES Admin
Structured as modular, intelligent IP and developed in close cooperation with the company Testonica within the framework of the GATE alliance program, these new ChipVORX models enable high-speed access tests for any kind of Random Access Memory (RAM) devices with full automation of the test development workflow. Users can utilise this new method to close significant holes in fault coverage affecting the test of modern electronics.
“In particular for the access test of the latest generation of DDR-SDRAM devices, traditional Boundary Scan practice is often problematic due to the stringent timing requirements of such memory devices. The new ChipVORX solution utilising FPGA embedded instruments provides a well-suited supplement,” notes Thomas Wenzel, Director of GOEPEL electronic’s JTAG/Boundary Scan Division. “Thanks to an exclusive cooperation with our partner Testonica we were able to completely integrate the new methodology into the automated workflow of our JTAG/Boundary Scan software platform SYSTEM CASCON, offering our customers another mature test strategy to work with.”

Artur Jutman, director of Testonica Lab adds: „We see ChipVORX as a whole new test platform that is tightly integrated with traditional Boundary Scan, opening up a new horizon for testability improvements. The enormous flexibility provided by FPGAs enables a range of test solutions that are limited only by the imagination. The new RAM Access Test IP is another milestone on the path towards an advanced JTAG-controlled embedded instrumentation platform.”

Due to the complete system integration of ChipVORX IP, the recognition of structural connections between the RAM targets and the FPGA as well as the test program generation (ATPG) and − in the case of detected defects − the pin-level diagnostics are fully automated. The test itself is based on access through a standard IEEE 1149.1 TAP (Test Access Port) and can be executed on any SYSTEM CASCON run-time station without additional options, with full support of Gang applications.
Since ChipVORX IP is target independent; the types of supported RAM devices are not limited. In addition to any kind of static RAM, modern DDR-SDRAM devices are supported. Since the same system libraries are utilised as with normal Boundary Scan based memory access tests, users can create new RAM models at any time, too.

Currently, ChipVORX models for RAM Access Test are available for all Altera and Xilinx FPGA families, with others in development. The use of ChipVORX IP does not require any background knowledge nor any special FPGA tools or recurring IP modifications. Through OEM cooperations with all leading vendors of In-Circuit Testers (ICT), Manufacturing Defect Analysers (MDA), Flying Probe Testers (FPT) and Functional Testers (FCT), this new ChipVORX based test solution is also available for manufacturing test systems integrating GOEPEL electronic’s Boundary Scan tools.

The new ChipVORX IP models will be supported starting with SYSTEM CASCON version 4.6 and will be enabled through the software’s license manager just like other SYSTEM CASCON tools. GOEPEL electronic’s professional JTAG/Boundary Scan development environment SYSTEM CASCON currently includes 45 completely integrated tools for in-system programming (ISP), test, debugging, and design validation. In terms of hardware, ChipVORX is supported by all SCANBOOSTER controllers as well as the platform SCANFLEX.

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