CCIX silicon demonstration vehicle in 7nm process technology

13th September 2017
Posted By : Alice Matthews
CCIX silicon demonstration vehicle in 7nm process technology

A collaboration to build the first Cache Coherent Interconnect for Accelerators (CCIX) test chip with TSMC 7nm FinFET process technology for delivery in 2018 has been announced by Xilinx, Arm, Cadence Design Systems, and TSMC. The test chip aims to provide a silicon proof point to demonstrate the capabilities of CCIX in enabling multi-core high-performance Arm CPUs working via a coherent fabric to off-chip FPGA accelerators.

Accelerating applications in the data centre is a growing requirement due to power and space constraints. Applications such as big data analytics, search, machine learning, wireless 4G/5G, in-memory database processing, video analytics, and network processing benefit from acceleration engines that move data seamlessly among the various system components. CCIX will allow components to access and process data irrespective of where it resides, without the need for complex programming environments.

CCIX will leverage existing server interconnect infrastructure and deliver higher bandwidth, lower latency and cache coherent access to shared memory. This will result in a significant improvement in the usability of accelerators and overall performance and efficiency of data centre platforms, lowering the barrier to entry into existing server systems and improving the total cost of ownership (TCO) of acceleration systems.

About the test chip
The test chip, implemented on TSMC’s 7nm process, will be based on the latest Arm DynamIQ technology, CMN-600 coherent on-chip bus and foundation IP. To validate the complete subsystem, Cadence provided key I/O and memory subsystems, which include the CCIX IP solution (controller and PHY), PCI Express 4.0/3.0 (PCIe-4/3) IP solution (controller and PHY), the DDR4 PHY, peripheral IPs such as I2C, SPI and QSPI, as well as associated IP drivers. Cadence verification and implementation tools are being used to build the test chip. The test chip provides connectivity to Xilinx’s 16nm Virtex UltraScale+ FPGAs over CCIX chip-to-chip coherent interconnect protocol.

Availability
The test chip will tape-out in early Q1 2018 with silicon availability expected in 2nd half 2018.

“As we work to innovate on advanced technology for compute acceleration, we are excited about the results of this collaboration,” said Victor Peng, COO at Xilinx. “Our Virtex UltraScale+ HBM family is built using TSMC’s 3rd generation CoWoS technology, which is now the industry standard assembly for HBM integration and cache-coherent acceleration with CCIX.”

“With the surge in artificial intelligence and big data, we’re seeing increasing demand for more heterogeneous compute across more applications,” said Noel Hurley, Vice President and General Manager, Infrastructure Group, Arm. “The test chip will not only demonstrate how the latest Arm technology with coherent multichip accelerators can scale across the data centre, but reinforces our commitment to solving the challenge of accessing data quickly and easily. This innovative and collaborative approach to coherent memory is a significant step forward in delivering high-performance, efficient data centre platforms.”

“By building an ecosystem for high-performance computing with our collaboration partners, we will enable our customers to quickly deploy innovative new architectures at 7nm and other advanced nodes for these growing data centre applications,” said Babu Mandava, Senior Vice President and General Manager of the IP Group at Cadence. “The CCIX industry standard will help drive the next generation of interconnect that provides the high-performance cache coherency that the market is demanding.”

“Artificial intelligence and deep learning will significantly impact industries including media, consumer electronics and healthcare,” said Dr. Cliff Hou, TSMC Vice President, Research & Development/Design and Technology Platform. “TSMC’s most advanced 7nm FinFET process technology provides high performance and low power benefits that satisfy distinct product requirements for High-Performance Computing (HPC) applications targeting these markets.”


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