Power

Space-sensitive design with negative input, negative output buck converters

29th June 2016
Caroline Hayes
0

An engineer designing a PCB, using voltage rails from elsewhere in the system has to convert the power available from those rails to the desired voltages with good efficiency, says Dr. Dan Tooth, Texas Instruments

If one or more of those rails are negative voltages, then converting them to other negative voltages may be useful to provide power to parts of the signal chain.

In an example design, it is supposed that VIN = -12V is available and the desired output is VOUT = -3V3, although other variations are possible. To perform the conversion, a boost converter IC is used in a buck topology (Figure 1). This topology can convert voltages for applications where VOUT is less than VIN. TPS61170 is the chosen boost converter IC, with an integrated MOSFET, switching at Fsw = 1.2MHz and in a 2.0 x 2.0mm QFN.

Feedback level-translator

From Figure 1, the output voltage is with respect to 0V, but the GND pin of the IC is connected to -VIN. A level translator is needed to translate the output voltage back to the feedback pin of the IC as the PNP transistor pair. In the steady-state and using KVL around the loop formed by the Vbes and the 3k3, gives that VOUT appears across the 3k3 causing 1mA to flow, as the Vbe’s almost cancel. The 1mA also flows through the 1k23 resistor, which drops 1.23V across it and this is the regulation voltage of the IC (FB = Vref = 1.23V). The 10k is chosen to also give ~1mA through transistor T2. The PNP transistor pair used is PMP5201Y,although other types will also work. A Bode plot simulation showed the level translator’s phase is almost flat out to at least 400kHz, before it will start to add phase lag into the system.

Figure 1: Negative VIN to negative VOUT converter using the PNP transistor pair level shifter; 1b, shows negative VIN to negative VOUT converter using the op amp current-source level shifter

Another feedback level translator uses an op amp plus MOSFET to derive a current source. VOUT (-3V3) is superimposed across the 3k3 resistor causing 1mA to flow, which drops 1.23V across the 1k23 resistor when in regulation. The op amp can be powered off 0V and –VIN. The common mode input voltage to the op amp can reach 0V (i.e. the positive rail), so the op amp must have a common-mode voltage range that allows this, such as a rail-rail input op amp like LM7341. Alternatively, if a positive rail (+Vcc more than or equal to 2.5V) is available in the system, then the op amp can be powered off +Vcc and –VIN, meaning an op amp like OPA172 can be used which does not have true rail-rail input common-mode voltage.

Control loop compensation

Although a boost converter IC is used, the conversion performed in this negative VIN/negative VOUT topology is a buck conversion and the buck power-stage and control laws apply. A simple approach to peak current mode compensation is valid as long as the desired cross-over frequency is not set too high, beyond which point the simple model starts to break down; a more sophisticated model is needed to accurately predict the gain/phase response. For TPS61170 a desired cross-over frequency of Fc = 1.2MHz / 50 = 24kHz was chosen. COUT is 22μF, de-rated to 20μF to allow for the DC bias voltage effect. The IC parameters for TPS61170 and other suitable ICs are shown in Figure 2.

An error amplifier high frequency zero cancellation capacitor was not fitted, as the COUT combined with its esr is at a very high frequency.

The chosen compensation components give a compensation pole Fp(ea) and zero Fz(ea) located at :

where Rea is the error amplifier output resistance. As expected, Fp(ea) is at a very low frequency. At Fz(ea), then the gain at that frequency, Gz(ea), is given by:

The power stage dominant pole F(ps) and the power stage dc gain G(ps) are given by:

The compensation, power stage and overall gain responses are shown in Figure 3. The phase margin is ~90°.

Simulation using TINA-TI

In Figure 1, the IC’s GND pin is connected to -VIN. This can pose an issue for simulation of the circuit, as IC simulation models, such as for TPS61170, are often written assuming that the IC model’s GND pin is connected to circuit node 0 and all the internal circuits inside the model connect directly to node 0, instead of the IC GND pin. To work around this issue, all the 0V (gnd) and -VIN voltage nodes in the actual circuit of Figure 1 are level-shifted by +VIN Volts. The IC GND pin that was at -VIN is now connected to 0V, the gnd nodes that were at 0V are now at +VIN. This level-shift makes no difference to the simulation results of the circuit and enables the simulation to run properly.

Test results

To test, the input capacitor CIN in Figure 1 should be placed directly between the IC’s GND pin and the free-wheel diode cathode. The feedback level-shift circuitry should be placed close to the FB pin of the IC. VOUT should be sensed using close-spaced parallel tracks that connect directly to the COUT pads. Figure 1b requires 100nF local decoupling for the op amp.

For both Figure 1a and 1b implementations, the start-up of the converter took 6ms and was monotonic with no overshoot. A resistive load of 11Ω was used (300mA) and another, parallel 11Ω load switched in/out to test the load transient response up to 600mA load. The load transient results for Figure 1a are shown in Figure 4 and show -3.34V ±100mV regulation accuracy. The results for Figure 1b were virtually identical at -3.39V ±100mV.

A higher current output of several amps can be supported by using TPS61175, or a higher current, using TPS55330, or a higher voltage and a higher current by using TPS55340. These operate in a similar manner to TPS61170. TPS61175, TPS55330 and TPS55340 have additional features: adjustable Fsw, Fsw synchronisation to an external clock and adjustable soft-start.

Figure 2: Datasheet parameters. (Automotive-grade device parameters may differ)

TPS61170-Q1, TPS61175-Q1 and TPS55340-Q1 are the available automotive AEC-Q100 versions. The schematics of the higher power ICs will be a copy of Figure 1, with the additional external components, the soft-start capacitor and frequency-set resistor, being connected to the AGND pin of the IC, along with the NC and SYNC pins. The EN pin is connected to 0V to permanently enable the IC, or a level shift circuit could be used to interface it to a logic control signal. The control loop can be designed in the same way as for the TPS61170, using the parameters in Figure 2 and the equations.

Low noise output

Should a very low noise output be required to power sensitive analogue loads, then the negative output from the negative DC/DC converter can be followed by a negative voltage LDO. For lower voltages then TPS723 (200mA, -2.7 to -10VIN) can be used, or for higher voltages, TPS7A30 (200mA, -3 to -36VIN) and TPS7A33 (1A, -3 to -36VIN) are recommended.

Figure 3: TINA-TI simulated power stage, compensation and overall gain responses

A small footprint negative VIN/negative VOUT buck converter was successfully designed, simulated and bench-tested using TPS61170. The TINA-TI simulation includes a work-around to deal with simulation models that have their internal circuits directly referenced to node 0, gnd. The simulation and practical results are in agreement with each other. Two feedback level shift circuits were shown to be effective. The same design approach is also applicable to three other higher-power ICs.

References
Designing a Negative Input Boost Converter from a Standard Positive Buck Converter by Mark Pieper, Texas Instruments Analog Applications Journal 2Q13
The Parallel Universe of Negative-Input Voltages by John Betten and Brian King, Power Electronics Technology, July 2008, p.32-35
Practical Implementation of Negative-Input, Negative-Output Step-down Switching Converters by Hector Arroyo, EETimes, July 27th 2007

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