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IDT Introduces industry-first programmable low power timing devices targeting portable consumer applications

30th March 2010
IDT
ES Admin
0
IDT announces the newest members of its IDT VersaClock family of timing devices. The VersaClock low power (LP) devices are programmable clock generators specifically designed to reduce power consumption and optimise board layout in battery-operated consumer applications including smart mobile handsets, personal navigation devices, MP3 players, camcorders, and other handheld applications.
The new timing devices offer a significant reduction in power consumption to meet the increasing demand for power efficiency in consumer electronic devices. The VersaClock LP devices help extend the battery life for today’s portable electronics by reducing the power requirement from 30-40mW to 4-8mW for a single clock output. The VersaClock LP solutions also significantly reduce the power usage during power down (20µW) and sleep mode with 32kHz clock active (200µW). These are new low power benchmarks for the industry.

The five new VersaClock LP devices (5P49EE801, 5P49EE802, 5P49EE601, 5P49EE602 and 5P49EE502) all feature four internal PLLs, each individually programmable and able to generate four unique frequencies, helping optimise the performance of each individual clock output and improving system accuracy. To give designers great flexibility, the frequencies can be generated from a clock input, a single TCXO or fundamental mode crystal reference. Using a single reference clock allows designers to simplify design and save board space while still maintaining accuracy.

One of the four internal PLLs supports spread spectrum generation which reduces electromagnetic interference (EMI), necessary for meeting the EMC certification requirements of global markets. Moreover, the new VersaClock devices can generate frequencies from 5kHz to 120MHz, which enables greater design flexibility for portable consumer applications. In addition, the devices are also compatible with many different output types — from single-ended LVCMOS to differential LVDS — to support various types of timing systems with a single device, simplifying design and optimising board layout.

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