Graphcore further implements machine-learning processor chip

With capabilities like automatic placement-clustering, advanced logic structuring, analytical clock-and-data optimisation and new algorithms for power optimisation, the latest release offers up to 5% better timing, 5% smaller area and 20% power savings.

Superior place-and-route technology has led to Graphcore, a UK-based artificial intelligence startup, to adopt IC Compiler II as their implementation platform for designing their first and ultra large, machine learning processor chip.

"We are designing a completely new type of processor – an Intelligent Processor Unit (IPU) designed to help customers accelerate the development of machine intelligence products and services," said Simon Knowles, CTO of Graphcore.

"With an extremely large design being built-from scratch, fast and predictable QoR throughout the design flow is key for our success. We believe IC Compiler II's powerful infrastructure and superior technologies will enable us to achieve our goals and bring our product to market on time."

The latest release of IC Compiler II provides key new technologies specifically targeted at increasing QoR, TTR, as well as advanced-node enablement. Concurrent Clock-and-Data (CCD) Optimisation, a key technology for high-performance designs, has been significantly enhanced with a new, solver-based, multi-objective engine capable of trading-off timing, area and power over an expanded solution space with minimal runtime impact.

CCD also benefits from new technology specifically focused on power reduction. Other optimisation technologies have been deployed in both the pre-route and post-route stages of design. During pre-route, enhanced global-route-based optimisation provides significantly improved pre- to post-route correlation with better timing.

In addition, advanced buffering for high-fanout nets improves QoR for the most challenging designs. Post-route, the optimisation has been enhanced with two key new technologies: optimisation driven by path-based analysis (PBA) and new advances in leakage power optimisation.

In addition to QoR, several new technologies have also been introduced to help accelerate TTR. For example, automatic placement clustering provides an optimised initial placement, leading to less variability between runs, and thus reducing the time needed to achieve an optimal placement.

Another example is automatic-max-density technology which increases productivity by automatically determining the targets for cell spreading during placement, providing optimal wire length, timing and congestion.

"IC Compiler II has rapidly established itself as the place-and-route solution of choice for high-performance designs, and the recent adoption by innovative startups like Graphcore exemplifies this trend," said Sassine Ghazi, Senior VP and Co-GM, Design Group at Synopsys.

"Key technology enhancements in the latest release of IC Compiler II focus on efficiently delivering excellent QoR for performance-critical designs, helping our customers get more differentiated products to market quickly."