Cortus announces Processor IP Roadmap for Embedded System on Chip (SoC) Applications

21st February 2012
Posted By : ES Admin
Cortus S.A. announces its plan to launch three new microcontroller IP cores as part of its processor roadmap. The new cores share common technology with the highly efficient APS3 core but address complementary market segments. The three new cores will be released over the coming six months.
With the use of sensor, control systems and connectivity technology becoming ubiquitous it is essential that integrated circuits for embedded applications combine adequate processing power, low energy usage and minimal silicon area. The Cortus APS3 has, since entering volume production in 2008, delivered industry-leading performance in terms of DMIPS/mW and DMIPS/mm2.



Michael Chapman, CEO Cortus, says “Although APS3 has been very successful in low power embedded applications such as SIM cards, Bluetooth LE, smart meters, encryption/decryption and touchscreen controllers, customers have been asking for a wider range of performance and complexity options”. He adds, “by mid 2012, Cortus will be able to supply microcontroller cores for applications ranging from high throughput floating point control systems down to programmable finite state machines as well as everything in between”.



Under the microcontroller core roadmap, the highly efficient APS3 will be complemented by two new integer and one floating point processor cores. The APS5 will support more complex processor sub-systems requiring caches, co-processors and multi-core architectures. The FPS6 single precision floating point microcontroller core will combine high floating point throughput with a small silicon footprint and low power dissipation.



For small microcontroller subsystems the Cortus will provide an entry-level 32-bit solution with the APS1 processor. This core, with a comparable silicon footprint to existing 8-bit cores such as 8051, will deliver greater computational performance and while dissipating much less power than 8-bit cores. APS1, like other Cortus processors, has been designed to be programmed with C or C++ without the need to use assembly code.



All Cortus cores share a common technology base with a modern RISC architecture and native 32-bit performance. They all can use the fast, low latency APS bus with Cortus peripherals. Cortus supplies a GNU-based APS toolchain and an Eclipse-based IDE which supports the entire product family. Ports of FreeRTOS, OpenRTOS and Micrium uC/OSII are available for the processor product range.



Cortus will be exhibiting from 28th February to 1st March on stand 5-143 at Embedded World 2012 in Nürnberg, Germany


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