The AD MUX I/O architecture introduces pin sharing between data and addresses, reducing the number of pins required by the memory chip and consequently adding cost savings for the microprocessor system. The additional savings will provide cellular phone manufacturers with a considerable competitive advantage, especially for mobile applications for which cost is an essential element in successful market penetration.
The AD MUX I/O architecture allows either an increase of data bus width with no pin count increase or a reduction in pin count without loss of performance. The smaller package mechanical dimensions than might otherwise be used, and the consequent reduction in printed-circuit board size, lowers costs for handset manufacturers.
These new devices are developed from existing and successful NOR Flash products. ST consistently provides optimum solutions in terms of technology developments, architectural structures, and advanced performances. Typically, the most advanced features are coupled with the highest performing applications, to provide specific end-user benefits. The introduction of the new AD MUX I/O series now ensures wide coverage of NOR Flash requirements across all segments of the mobile phone market.
The AD MUX I/O portfolio includes both standalone and subsystem solutions, based on one-bit and two-bit-per-cell technology, which accommodates increasing memory density with optimized die size in 130nm and 90nm manufacturing technologies. The family offers Burst Mode and Multiple Bank architectures, and are available in LFBGA88 (8x10mm), LFBGA107 (8x11mm), or VFBGA44 (7.5x5mm) packages.
The standalone NOR Flash memories range from 16- to 64-Mbit densities in one-bit-per-cell technology, and from 128- to 256-Mbit densities in two-bit-per-cell technology.