FPGAs

KaiSemi Will Showcase its Zero NRE Automated FPGA-to-ASIC Replacement at ESC Silicon Valley

24th March 2011
Staff Reporter
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KaiSemi Ltd., a fabless semiconductor vendor, announced that it will exhibit at the Embedded Systems Conference (ESC) Silicon Valley 2011, being held May 3-5 at the McEnery Convention Center in San Jose, California.

KaiSemi is set to showcase its innovative IP synthesis tool that automatically converts any FPGA netlist directly to ASIC netlist with the push of a button. Based on its unique tool, KaiSemi provides a seamless full turnkey 1-to-1 ASIC replacement. KaiSemi delivers a reduced cost ASIC replacement to any existing FPGA product, based on standard-cell fab processes.

Backed by a tier-one fab vendor, KaiSemi's automated conversion and flow eliminates the need for customer involvement and resources, while enabling short lead times and deep cost optimization. Compared to traditional ASIC flow, in KaiSemi's FPGA-to-ASIC conversion flow, the customer risk is eliminated through the company's obligation to a conversion with a functional guarantee, combined with a zero NRE model for minimum quantities.

KaiSemi's automated conversion, combined with a full turnkey ASIC and manufacturing flow up to production shipments, is set to reduce the relevant FPGAs' unit price by at least 50%, including the NRE amortization.

In addition to its FPGA-to-ASIC solution, KaiSemi will exhibit its conversion-based replacement solutions in the areas of multi FPGA/peripherals-to-ASIC, ASIC-to-ASIC, DSP-algorithm-to-ASIC, FPGA-to-FPGA and End-of-Life.

Since the official launch at Electronica 2010 in Munich, Germany, the interest in KaiSemi's solutions encouraged the company to establish a network of distributors in America, Europe and Asia.

KaiSemi's automated FPGA-to-ASIC tool minimizes silicon area costs and selects the most optimized standard-cell fab processes and libraries out of a preinstalled embedded database of multiple standard-cell fab processes and libraries, and a pre-assigned set of a functional FPGA replacements database. The company's technology reduces customer costs, while achieving a fast ASIC cycle time through a guaranteed seamless process that does not involve the customers' designers.

Compared to ASICs, FPGAs involve much higher unit costs and much lower upfront costs, said Tomer Kabakov, VP Sales and Marketing at KaiSemi. While some companies invest less in upfront cost and use FPGA as a final product, others invest in the upfront traditional ASIC flow cost and use ASIC as a product. KaiSemi's seamless automated FPGA to ASIC replacement is appropriate for both types of customers. Whether reducing FPGA unit cost or eliminating the upfront costs targeting ASIC. KaiSemi's technology is unique in relation to standard-cell ASIC processes and there are no competitors that use the same technology.

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