FPGA engineering samples offer up to 50% lower power

Posted By : Alice Matthews
FPGA engineering samples offer up to 50% lower power

Provider of semiconductor solutions differentiated by power, security, reliability and performance, Microsemi, has announced its PolarFire field programmable gate array (FPGA) engineering samples (ES) are available for ordering. The PolarFire FPGA family provides the lowest power, cost-optimised mid-range devices spanning from 100K logic elements (LEs) to 500K LEs. Its PolarFire Evaluation Kit, already shipping to key customers, is also available for ordering from the company and its distribution channels.

In addition, Microsemi’s Libero SoC PolarFire Design Suite has been updated with version 1.1 Service Pack 1 enabling design starts for the broad customer base, together with key quick start demonstration designs for rapid evaluation and prototyping.

Microsemi’s PolarFire FPGA ES devices, which feature 12.7G transceivers and offer up to 50% lower power than competing mid-range FPGAs, have shipped to early access programme (EAP) customers since February and are now available for all customers. The FPGA product family is suitable for a wide range of applications within wireline access networks and cellular infrastructure, defense and commercial aviation markets, as well as industry 4.0 which includes the industrial automation and Internet of Things (IoT) markets.

“After successfully shipping initial ES devices and hardware kits in February to our early access and select tier-one customers for system integration and advanced evaluation, we are pleased to reach another key milestone in the PolarFire family rollout by making ES and a high-performance evaluation platform available to our broader customer base,” said Shakeel Peera, Senior Director of SoC product marketing, at Microsemi. “The release of the evaluation kit allows customers to port complex designs and test out advanced features - including 12Gbps package protocols, high-speed DDR3/4 memory interfaces and general purpose input/outputs (IOs) - as well as complex signal and waveform processing, all in the industry's lowest power, cost-optimised midrange FPGA.”

Multiple demo reference designs are available now with full design files for Libero SoC PolarFire targeting the PolarFire Evaluation Kit, including JESD204B Interface, PCI Express (PCIe) Endpoint, 10GBASE-R Ethernet Loopback, DSP FIR Filter and Multi-Rate Transceiver Demo, with additional reference designs planned over the coming months.

Microsemi's PolarFire Evaluation Kit is a comprehensive platform for evaluating the company’s recently introduced PolarFire FPGAs and is well-suited for high-speed transceiver evaluation, 10Gb Ethernet, IEEE 1588, JESD204B, Synchronous Ethernet (SyncE) and CPRI. The solution is also suitable for a wide variety of end markets and applications, including communications (high-speed transceiver evaluation, full-duplex 12.7 Gbps SerDes channel testing, SyncE and 1588 applications, and dual Gigabit Ethernet RJ45 solutions), industrial (PCIe edge testing, and SyncE and 1588 applications), and aerospace and defense (encryption and root-of-trust, secure wireless communications applications, aircraft networking, and actuation and control). The kit features a high-pin-count FPGA mezzanine card (FMC), numerous surface mount assemblies (SMAs), PCIe, dual Gigabit Ethernet RJ45, small form-factor pluggable (SFP) modules, DDR4 and USB.

Offering additional design support for customers, Microsemi’s Libero SoC PolarFire Design Suite provides high productivity with its comprehensive, easy to learn, easy to adopt development tools for designing with Microsemi’s PolarFire FPGAs. The suite includes a complete design flow with Synopsys SynplifyPro synthesis and Mentor Graphics ModelSim mixed-language simulation with best-in-class constraints management, as well as Microsemi’s differentiated FPGA debugging suite, SmartDebug. The SmartDebug tool enables hardware debugging using the in-built dedicated signal probe and offers advantages including live on-chip debugging, eliminating extra FPGA resources, reduced FPGA design debug cycles and enabling read-write capability to LEs and memory blocks. The release of v1.1 SP1 includes faster run time, DDR3 support, and support for advanced 10 Gbps transceiver based protocols, as well as IBIS Algorithmic Modeling Interface (AMI) models for advanced simulation of signal integrity.

Key features:

  • 300K LE PolarFire FPGA in an FCG1152 package (MPF300TS-1FCG1152I)
  • HPC FMC connector
  • 1x SFP+ cage
  • IEEE1588 phase-locked loop (PLL)
  • SMA connectors for testing of full-duplex 12.7Gbps SerDes channel
  • 4GB DDR4 x32 and 2GB DDR3 x16
  • PCI Express (x4) edge connector
  • 2 x RJ45 for 10/100/1000 Ethernet using serial gigabit media-independent interface (SGMII) on general purpose input/output (GPIO)
  • Dual 10/100/1,000 BASE-T PHY (VSC8575) for SyncE and 1588 application
  • Power management unit for 1 or 1.05V PolarFire FPGA core voltage
  • USB to universal asynchronous receiver/transmitter (UART) interface
  • Embedded programming and debugging using serial peripheral interface (SPI) and Joint Test Action Group (JTAG)
  • On-board power monitoring
  • 2 x 1Gb SPI flash memory.

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