Verification platform reduces IP development time

17th May 2017
Posted By : Alice Matthews
Verification platform reduces IP development time

Cadence Design Systems has announced the expansion of its JasperGold Formal Verification Platform with the introduction of the JasperGold Superlint and Clock Domain Crossing (CDC) Apps, advanced formal-based technologies that address register-transfer level (RTL) signoff requirements. The Superlint and CDC Apps bring the power of JasperGold formal technology to the RTL designer’s desktop.

The new apps improve IP design quality by reducing late-stage RTL changes by up to 80% and, the company claims, by reducing IP development time by up to four weeks when compared to existing verification solutions.

With today’s larger, more complex designs, there is a growing need to develop robust IP that can be reused in multiple SoCs to improve designer productivity. Signoff checks that were previously performed at the netlist implementation stage now need to be performed on the RTL design. Traditional static lint and CDC tools have not been effective at ensuring that the RTL code is of the highest quality.

With the delivery of the latest JasperGold formal-based RTL signoff technologies, designers have access to richer functional checks and formal-powered intelligent debugging to reduce violation noise, which is one of the most pressing RTL signoff challenges today. The JasperGold Superlint and CDC Apps are fully integrated with the powerful JasperGold Visualize debug environment, utilising proven formal intelligence to increase debug efficiency for RTL designs. Additionally, both apps incorporate Cadence’s existing formal capabilities to improve waiver handling. Designers can now perform signoff with robust, reusable and CDC-clean RTL code in the verification and implementation phase, shortening overall time to market and significantly improving design quality.

“Ever-increasing project schedule and IP quality pressures make effective RTL signoff an important part of the development process,” said Dr. Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Building upon the proven JasperGold platform, Cadence is bringing its industry-leading formal technology to RTL signoff, giving logic designers the ability to develop more robust and reusable IP code in a significantly shorter amount of time.”

In the new Superlint App, Cadence has combined traditional RTL linting and formal verification capabilities, deriving the most complete set of functional checks from the RTL automatically. Similarly, the CDC App offers a metastability injection flow for rigorous CDC verification in either the Cadence JasperGold formal or Xcelium Parallel Simulator environments for more comprehensive signoff.


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