Design for test tool shrinks manufacturing costs

"Using DFTMAX Ultra, we implemented test compression into a mixed-signal design in just a few hours and successfully tested the manufactured parts," said Mark Tyndall, senior vice-president of Corporate Development and Strategy, general manager of the Power Conversion Business Group, Dialog Semiconductor. "We observed DFTMAX Ultra reduce test time by 3X and more compared to our previous compression technology and require few device pins."

DFTMAX Ultra efficiently streams compressed test data in and out of the design-for-test circuitry, significantly lowering the amount of data required to achieve high manufacturing test quality of silicon parts.  The tool-generated architecture requires fewer test pins and enables silicon parts to operate at higher frequencies while in test mode. As a result, engineers can test more die in parallel and reduce the time required to test each die. For superior quality of results and faster turnaround time, DFTMAX Ultra is built into Design Compiler and linked with TetraMAX ATPG and the Synopsys Galaxy™ Design Platform suite of tools, concurrently optimizing for speed, area, power, test and yield.

"Success with DFTMAX Ultra on silicon parts underscores Synopsys' commitment to helping customers meet their most demanding test quality and cost requirements," said Bijan Kiani, vice president of marketing in Synopsys' Design Group.