Non volatile memory IP cuts time to market
Synopsys has availability of the silicon-proven DesignWare AEON Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP for TowerJazz 180-nanometer (nm) SL process technology. The NVM IP integrates high voltage generation and control circuitry using a standard CMOS technology without the need for additional masks or processing steps.
The IP operates from a single core supply, eliminating the complication of providing a separate voltage for NVM programming. The DesignWare AEON FTP Trim NVM IP provides the smallest area for precision analogue IC trimming and sensor calibration applications, in a similar footprint as one-time programmable (OTP) solutions with the advantage of reprogrammability.
The reprogrammability advantage of the NVM IP enables designers to make in-field calibration updates, which allow end customers to make customizations and changes. The NVM IP includes necessary support and control circuitry including all high voltage generation and distribution required for programming to reduce system design complexity and IC area. It also supports up to 1 k bit instances, up to 10,000 write cycles, and more than 10 years of data retention at a temperature range (-40 degrees C to +125 degrees C) for industrial applications.
“Synopsys DesignWare AEON FTP Trim NVM IP enabled us to meet our customers' aggressive schedule requirements and need for small reprogrammable non-volatile memory IP in the TowerJazz 180-nanometer process technology," said Tal Bar (Dotan), director of IP Design Services at TowerJazz. "The combination of Synopsys' trusted IP solution and TowerJazz's IC manufacturing capabilities helps our mutual customers achieve their design goals faster and with less integration risk."
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