Place and route tool accelerates turn-around-time

31st October 2014

Synopsys Inc

Mick Elliott

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Panasonic’s LSI Business Division has achieved first time working silicon using the Synopsys IC Compiler II designed for high-performance multimedia design in 40-nm technology. Compiler II offers 5X faster design implementation that enables faster turn-around-time for large partitions. It has the ability to seamlessly handle more modes and corners drastically improves signoff convergence and reduces ECO iterations.

Unveiled at Synopsys User Group (SNUG) in Silicon Valley earlier this year, IC Compiler II is a successor to the IC Compiler product.

Key capabilities in IC Compiler II include rapid design exploration, unique new clock-building, analytics-driven optimisation to boost quality-of-results and extensive use of multi-mode and multi-corner optimisation throughout the flow to accelerate turnaround time. Compiler II is now seeing expanded use to other designs at 40 nanometer (nm) and 28 nm process technology nodes.

"IC Compiler II was instrumental in enabling us to hit our market window and achieve silicon success for our complex multimedia chip. We are now entering volume production," said Hiroki Tomoshige, general manager at Panasonic Corporation System LSI Business Division, Division 3, Second Development Group. "We are very pleased with the breakthrough performance IC Compiler II has delivered to shorten our design cycles and get our competitive products to market faster."

IC Compiler II was built from the ground up to deliver a major leap forward in physical design productivity.

Based on a new multi-everything infrastructure and multicore technology that enables ultra-high-capacity design planning capability, unique clocking technology and advanced global and analytical closure techniques, IC Compiler II delivers a groundbreaking 10-times increase in design throughput. IC Complier II's "analytically-global" optimisation provides faster, broader and more convergent physical synthesis and closure.

This natively multi-threaded technique utilizes new, highly scalable timing and extraction engines that enable extensive multi-corner and multi-mode (MCMM) optimisation. Early and broad analysis enables optimization for large number of concurrent scenarios, improving signoff convergence and reducing ECO iterations to a minimum.

Additionally, patent-pending MCMM-aware local-skew clock construction techniques enable significant speed up in the building of complex clock networks with hundreds of domains and achieve the high-frequency clock requirements that are typical for the success of high-end chips.