The Process of FPGA Design Takes Giant Leap Forward With the New Stellar IP Tool from 4DSP

In recent years, the substantial growth of resources available inside FPGA devices has forced engineers to change the way they approach programmable logic design. A higher level of abstraction and the removal of error prone tasks are critical to the success and timely completion of projects. FPGA technology has often been decried in the past for its implementation slowness from concept to release. Relying on existing IP to speed up this process has become essential and ensures that the FPGA portion of the system does not become the schedule bottleneck. Stellar IP does not claim it will solve all inherent problems of FPGA design but it guarantees that its simplicity of use will help engineers complete their project faster by removing tedious steps out of the cycle.

Knowledge of a HDL language is not required for using Stellar IP. This provides software engineers with the ability to create new FPGA designs by relying on existing IP and extend their domain of influence to the entire system.

“Programming a software for a Stellar IP based design is as simple as using a microcontroller. Designing a StellarIP FPGA firmware is even easier since it’s only about interconnecting IP blocks to one another, either by using a text file or a graphical schematics editor. The tool takes care of the rest and prevents the user from having to deal with the intricacies of FPGA design” said Arnaud Maye, Embedded Systems Manager at 4DSP.

Stellar IP offers many benefits such as simplifying the integration of new cores that can be reused across multiple designs. It provides a library of off-the-shelf IP cores and automates the creation and compilation of ISE projects in addition to simulation scripts.

Stellar IP is available for free as part of the 4DSP Board Support Package targeting the 4DSP FMC and Virtex-6 FPGA product lines