Lattice Announces Updates And Enhancements To Its FPGA Design Tool Suite

“Service Pack 1 enhances and extends design support of the LatticeECP3 family to enable users to achieve low cost, low power design goals. More specifically, this important update allows users of the ECP3-150EA device to design with even greater confidence that the board-level behavior of their design, such as power and timing, will match what the tools report,” said Mike Kendrick, Lattice’s Manager of Software Product Planning. “SP1 also further boosts DSP application performance in the LatticeECP3 devices.”

Service Pack 1 updates the device values to production characterized silicon for the LatticeECP3-150EA device. With SP1, static timing analysis, timing simulation and power calculation will report results that even more accurately reflect the behavior of the actual production device. Moreover, PCS/SERDES calibration settings used for the supported IO protocols have been tuned to provide more robust behavior. HDL generation of generic DDR interfaces from the IPexpress™ tool, first introduced in ispLEVER 8.0, has been enhanced to include two additional interfaces, resulting in more design and implementation flexibility. There is also additional flexibility in the choice of pins for generic DDR interfaces. Synplify Pro® synthesis has added several enhancements, allowing higher performance and lower utilization in DSP-centric applications by further exploiting the unique sysDSP™ Block cascading capability.