NXP and ON Semiconductor to Offer New KNX Evaluation Board for Power Efficient Design of Twisted Pair Building Automation Networks

19th April 2012
Written by : ES Admin
ON Semiconductor and NXP Semiconductors N.V. have introduced an evaluation board and complete reference design for power efficient Twisted Pair (TP) networks. The evaluation board, which will be available in May, is undergoing the final phases of formal KNX certification.
“This new twisted pair networks development board has been specifically designed to assist building automation customers by simplifying their design process with a ready-to-implement, energy efficient KNX TP solution for applications such as lighting switches and control, HVAC control, shutters and occupancy detection,” said Ryan Cameron, vice president of Industrial and Timing products for ON Semiconductor. “By teaming up with NXP, we were able to jointly create a complete, highly power efficient solution that enables customers to reduce both their development costs and time to market for KNX applications based on Cortex-M processor family.”

“The stability and flexibility of KNX make it a tremendously popular choice for intelligent wired home and building automation networks. This evaluation board will help developers create cost-efficient KNX designs very quickly, while taking advantage of the very low active power consumption of the NXP Cortex-M0 microcontroller, as well as its powerful 32-bit architecture,” said Jan Willem Vogel, senior director of marketing, Appliances, Energy and Automation segment, NXP Semiconductors.

ON Semiconductor is demonstrating the KNX TP evaluation board and reference design this week in Frankfurt, Germany, at the Light+Building 2012 show. Please visit us at the KNX member’s booth located in Hall 8 at stand F98.

The TP evaluation board and reference design features NXP’s low-power Cortex-M0 microcontroller and ON Semiconductor’s soon to be launched NCN5120 receiver-transmitter IC.

• The first evaluation boards will be available with the NXP LPC1227 microcontroller. Based on the ARM® Cortex™-M0 processor – the smallest, most energy-efficient 32-bit core available today – NXP’s LPC1100 and LPC1200 microcontrollers provide compelling solutions for home and building automation products. The LPC1100 and LPC1200 series include up to 128 KB Flash and 8 KB SRAM, and offer configurable peripherals ideally suited for energy-efficient controls and KNX nodes. Because of their low power consumption, these devices can be powered directly from the DC-DC converter of the NCN5120, making bus-powered devices easy to implement. With performance levels up to 45 DMIPS, a single NXP Cortex-M0 microcontroller delivers the resources required to run a KNX stack, with enough bandwidth available for the end application. A certified implementation of the KNX System B is now available for the LPC1200 at Weinzierl Engineering.

• ON Semiconductor’s NCN5120 receiver-transmitter IC is suitable for use in KNX twisted pair networks (KNX TP1-256). It supports the connection of actuators, sensors, microcontrollers, switches or other applications in a building network. The NCN5120 will be the first product in a family of KNX transceivers designed to handle the transmission and reception of data on the bus. Featuring built-in mixed-signal technology, the NCN5120 integrates the analog front end, digital processing capability and power supply features in a monolithic integrated circuit. It provides a 20 volt (V) regulator and two high efficient DC-DC converters generating a fixed 3.3 V and an adjustable 3.3 V to 21 V regulated voltage from the bus with 100 milliamp (mA) drive capability each. This transceiver is ideal for high power applications and has been designed to reduce the bill of materials while still supporting safe and reliable coupling to the bus thanks to features such as selectable fan-in mode, bus voltage and temperature monitoring. Device samples of the NCN5120 are available upon request. KNX certification of the device is in the final phases.

Full production of the device is expected to start during the third quarter of 2012.

Availability
The TP evaluation board and reference design will be available for ordering from NXP starting in May 2012.

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