IP solution offers 300GB/s bandwidth for graphics SoCs

3rd August 2017
Posted By : Alice Matthews
IP solution offers 300GB/s bandwidth for graphics SoCs

Provider of high-quality, silicon-proven IP solutions for SoC designs, Synopsys, has introduced its complete DesignWare High Bandwidth Memory 2 (HBM2) IP solution consisting of controller, PHY and verification IP, enabling designers to achieve up to 307GB/s aggregate bandwidth, which is 12 times the bandwidth of a DDR4 interface operating at 3,200Mb/s data rate. In addition, the DesignWare HBM2 IP solution delivers approximately ten times better energy efficiency than DDR4.

Advanced graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the increasing compute performance brought by advanced process technologies.

With the DesignWare HBM2 IP solution, designers can achieve their memory throughput requirements with minimal power consumption and low latency. The new DesignWare HBM2 IP solution is built on Synopsys' silicon-proven HBM and DDR4 IP, which has been validated in hundreds of designs and shipped in millions of systems-on-chips (SoCs), enabling designers to lower integration risk and accelerate adoption of the new standard.

"We selected Synopsys' DesignWare HBM2 IP solution to take full advantage of the bandwidth and power efficiency of the 16GB of HBM2 memory in our Radeon Vega Frontier Edition graphics cards," said Joe Macri, Corporate Vice President and product CTO at AMD. "Synopsys' deep expertise in memory interfaces enabled us to successfully integrate HBM2 IP into the 'Vega' GPU architecture and achieve aggressive power and memory bandwidth targets to serve machine learning and advanced graphics applications."

The complete DesignWare HBM2 IP solution enables designers to achieve their memory bandwidth, latency and power objectives. The DesignWare HBM2 Controller supports pseudo-channel operation in either lock step or memory interleaved mode, allowing users to maximise bandwidth based on their unique traffic pattern. Both the HBM2 controller and PHY utilise a DFI 4.0-compatible interface to simplify integration with custom DFI-compliant controllers and PHYs.

The DesignWare HBM2 PHY IP offers four trained power management states and fast frequency switching that allows the SoC to manage power consumption by quickly changing between operating frequencies. The DesignWare HBM2 PHY enables a microbump array that matches the JEDEC HBM2 SDRAM standard for the shortest possible 2.5D package routes and highest signal integrity. To simplify HBM2 SDRAM testing, the DesignWare HBM2 PHY IP provides an IEEE 1500 port with an access loopback mode for testing and training the link between the SoC and HBM2 SDRAM.

Synopsys VC Verification IP for HBM is fully compliant to HBM JEDEC specification (including HBM2) and provides protocol, methodology, verification and productivity features including built-in protocol checks, coverage and verification plans, and Verdi® protocol-aware debug and performance analysis, enabling users to achieve rapid verification of HBM-based designs.

"Increasing memory bandwidth without overtaxing power and area budgets is critical for graphics, HPC and networking applications," said John Koeter, Vice President of marketing for IP at Synopsys. "As the leading providing of memory IP, Synopsys has engaged closely with several lead customers to develop an HBM2 IP solution that enables designers to address increasing throughput requirements, with improved latency and power efficiency for their high-performance SoC designs."

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