Integrated memory design and verification solution

Posted By : Alice Matthews
Integrated memory design and verification solution

An integrated solution for memory design and verification has been announced by Cadence Design Systems. The Legato Memory Solution eliminates the complexity of piecing together point tools for multiple design and verification tasks and can lead to productivity gains of up to two times when compared with previous point tool offerings. The first-of-its-kind Legato Memory Solution’s cohesive design environment automates design steps and lets customers use the innovative Cadence toolset to deliver products to market faster. 

The solution includes new patent-pending Cadence Super Sweep technology that utilises existing simulation databases for multi-corner and Monte Carlo analysis, allowing customers to improve both runtime and simulation throughput.

The technology capabilities included with the Cadence Legato Memory Solution improve overall design productivity and are as follows:

  • Bitcell design and verification environment: Customers can design the bitcell, including variation analysis, without ever having to leave the design environment.
  • Memory compiler design and verification environment: Customers can design and verify full memory arrays within the Legato Memory Solution and access the new Super Sweep technology to maximise accuracy and simulation throughput for advanced-node designs.
  • Memory characterisation environment: Customers can create Liberty format models of the memory for system-on-chip (SoC) full-chip analysis. The tight integration between memory characterisation and circuit simulation provides additional accuracy and performance improvements that can’t be achieved by point tools.

“As a world-leading supplier of System-on-Chip solutions, focused on imaging, networking and computing technologies that drive a wide variety of applications, it is critical that we accurately simulate memory instances to minimise area and power consumption of System-on-Chip,” said Yoshifumi Okamoto, Corporate Executive Vice President & CTO at Socionext. “Through our use of the Cadence Legato Memory Solution, we have experienced a two times productivity gain when compared with our point solution and successfully taped out 12nm memory macro designs for our System-on-Chip solutions, and we can confirm good correlation between simulation result and silicon measurement.”

“Long simulation times and a high rate of inaccuracy have become bottlenecks in the SoC design cycle schedule,” said Tom Beckley, Senior Vice President and General Manager of the Custom IC & PCB Group at Cadence. “The new Legato Memory Solution combines patented technologies interleaved with our existing, proven Virtuoso Liberate MX Memory Characterisation Solution, Spectre eXtensive Partitioning Simulator (XPS) and Virtuoso Variation Analysis solutions to improve designer productivity and enable our customers to meet stringent design schedules.”

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