Design

IC prototyping service provides cost savings & flexibility

17th November 2014
Siobhan O'Gorman
0

The Multi-Project Wafer (MPW) or shuttle run IC prototyping service from the Full Service Foundry division of ams is now available with an updated schedule for 2015. Combining several designs from different customers onto a single wafer, the service offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among a number of different shuttle participants.

As a further extension of its ‘More than Silicon’ initiative, ams now provides advanced packaging services to its shuttle participants by offering Wafer Level Chip Scale Packaging on selected MPW runs within 2015. This unique combination of fast prototyping service plus chip scale packaging offers large cost savings and flexibility to foundry customers.

ams’ MPW service includes the whole range of 0.18 and 0.35μm specialty processes. In order to provide leading analogue semiconductor process technologies, manufacturing and services, ams offers four MPW runs in 0.18μm CMOS (C18) process as well as four MPW runs in its advanced 0.18μm High-Voltage CMOS (H18) technology supporting 1.8, 5, 20 and 50V devices. For 0.35μm processes, which are based on the 0.35μm CMOS process transferred from Taiwan Semiconductor Manufacturing Company, a total of 14 runs are offered in 2015. ams' 0.35μm High-Voltage CMOS process family, optimised for high-voltage designs in automotive and industrial applications, supports 20, 50 and 120V devices. The advanced High-Voltage CMOS process with embedded EEPROM functionality as well as the 0.35μm SiGe-BiCMOS technology S35 are fully compatible to the base CMOS base process and complete ams’ MPW service portfolio.

Overall, ams will offer almost 150 MPW start dates in 2015, enabled by long lasting co-operations with partner organisations such as CMP, Europractice, Fraunhofer IIS and Mosis.

To take advantage of the MPW service, ams’ foundry customers deliver their completed GDSII-data on specific dates and receive untested packaged samples or dies within a short lead-time of typically 8 weeks for CMOS and 12 weeks for High-Voltage CMOS, SiGe-BiCMOS and Embedded Flash processes.

All process technologies are supported by the well-known hitkit, ams’ industry benchmark process design kit, based on Cadence, Mentor Graphics or Keysight ADS design environments. The hitkit comes complete with fully silicon-qualified standard cells, periphery cells and general purpose analogue cells such as comparators, operational amplifiers, low power ADCs and DACs. Custom analogue and RF devices, physical verification rule sets for Assura and Calibre, as well as precisely characterised circuit simulation models, enable rapid design starts of complex high performance mixed-signal ICs. In addition to standard prototype services, ams also offers advanced analogue IP blocks, a memory (RAM/ROM) generation service and packaging services in ceramic or plastic.

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