Design

Faraday Technology selects PLL from Silicon Creations

22nd July 2014
Siobhan O'Gorman
0

Silicon Creations has announced that Faraday Technology has selected its UMC 55nm SP Phase-Locked Loop (PLL) IP for its SoC design in multimedia and consumer related applications. The PLL has ranges of 1MHz-1.2GHz input and 1.5MHz-2.4GHz output as well as a 24-bit fractional modulator, allowing output frequency steps below 0.01ppm.

With an integrated jitter compensation Digital-to-Analogue Converter (DAC), Silicon Creations claims that the output long-term jitter in fractional mode of their PLL IP is better than most integer PLLs. The company also claim that their PLL IP ensures satisfying result specific SoC clocking applications, as it has the capability to generate digitally exact spread spectrum modulation.

“In the consumer and multimedia market, Faraday has accumulated the solid domain know-how and service experience. Besides our self-developed IPs, Faraday further extend the partnership to some professional IP vendors for an even more comprehensive offering,” says Jensen Yen, Associate Vice President of Marketing and Spokesperson, Faraday. “By leveraging Silicon Creations’ expertise and its technical support, Faraday can assist customers to launch their solutions, with less design and integration effort, and in most aggressive schedule,” he added.

“We are glad that Silicon Creations’ PLL has been selected for Faraday’s exacting requirements and commitment to providing the most sophisticated design service and technologies,” says Andrew Cole, Vice President of Business Development, Silicon Creations. “We believe that our PLL will help Faraday to provide its high-performance SoCs within a short schedule.”

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