This was implemented with the low-power design methodology covering power-gating and memory retention, IEEE 1801 UPF2.1 power intent, and statistical on-chip variation (SOCV)-based timing closure using the Liberty Variation Format (LVF) library.
The Cadence digital and signoff tools met all of Samsung’s accuracy requirements, enabling foundry customers to quickly achieve design closure and deliver large, complex FinFET designs faster with the 10LPP process. In addition, the Cadence signoff tools have been certified for tapeout using Samsung’s certification criteria for baseline accuracy.
The tools in the design flow include:
- Innovus Implementation System: Based on a massively parallel architecture, it enables larger designs and reduced turnaround time while supporting Samsung’s 10LPP design requirements, such as floorplanning, placement and routing with integrated colour-/pin-access /variability-aware timing closure, and clock tree and power optimisation
- Genus Synthesis Solution: Delivers improved productivity during Register-Transfer Level (RTL) design and highly correlated, optimal Quality of Results (QoR) in final implementation
- Quantus QRC Extraction Solution: Offers best-in-class accuracy versus foundry baseline; faster, scalable cell-level and transistor-level extraction; multi-patterning; multi-colouring; and a built-in 3D extraction capability, Quantus Field Solver (FS)
- Conformal Logic Equivalence Checking (LEC): Ensures the correctness of logic changes and Engineering Change Orders (ECOs) as well as the implementation flow, while enabling the comparison of different views/abstraction levels
- Conformal Low Power: Enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs
- Tempus Timing Signoff Solution: Provides integrated, advanced process delay calculation and Static Timing Analysis (STA) that achieves Samsung’s accuracy requirements, including those at low voltage operation
- Voltus IC Power Integrity Solution: Cell-level power integrity tool that supports comprehensive ElectroMigration and IR drop (EM/IR) design rules and requirements while providing full-chip System-on-Chip (SoC) power signoff accuracy
- Physical Verification System: Includes advanced technologies and rule decks to support Design Rule Checking (DRC), Layout Versus Schematic (LVS), smart metal fill, yield scoring, voltage-dependent checks, and in-design signoff
- Litho Physical Analyser: Enables designers to detect and automatically repair process hotspots to improve design manufacturability and yield of digital, custom and mixed-signal designs, libraries and IP. This is part of Samsung’s foundry DFM offering.
- Cadence CMP Predictor: Predicts the 3D topology variation and hotspots caused by Chemical Mechanical Polishing (CMP) to improve design manufacturability and reduce topology variation. This is part of Samsung’s foundry DFM offering.
- LDE Electrical Analyser: Allows Layout-Dependent Effect- (LDE-) aware re-simulation, layout analysis, matching constraint checking, reporting on LDE contributions, and the generation of fixing guidelines from partial layout to accelerate analogue design convergence
- Modus Test Solution: Provides scan and logic/memory Built-In Self Test (BIST) insertion, combined with a physically aware 2D Elastic Compression architecture, enabling design engineers to achieve reductions in test time to minimise production test cost
”Samsung and Cadence collaborated closely on this 10LPP process reference flow to provide our mutual customers with a fast path to design closure,” said Jaehong Park, Senior Vice President of the Design Service Team at Samsung Electronics."Cadence’s digital and signoff tools have implemented methodology innovations that enable designers to access and reap the benefits of our 10LPP process.”
"Samsung’s certification of the Cadence digital tools enables customers to manage and overcome complexity and deliver advanced 10LPP designs faster,” said Dr. Anirudh Devgan, Senior Vice President and General Manager of the Digital and Signoff Group and the System and Verification Group at Cadence. ”Customers using the Cadence flow on Samsung’s latest 10LPP process can also achieve optimal Power, Performance and Area (PPA) to meet their aggressive time-to-market requirements.”