Cadence tools reduce leakage power by 50% in smartphone chip
Yamaha has used components of the Cadence Low-Power Solution to achieve a 50% reduction in leakage power in its latest chip for smartphones. Yamaha selected Cadence Encounter RTL Compiler, Cadence Encounter Conformal Low Power and Cadence Encounter Digital Implementation System.
The Cadence Low-Power Solution supports many advanced low-power techniques such as multi-supply voltage, power shutoff and multi-bit cell inferencing, which are critical to reducing power. In addition to reducing leakage power, Yamaha utilised the solution to achieve design closure at the target performance and power levels. The design tools in the solution support a consistent power management intent as described in the Common Power Format for all design phases such as implementation and verification from register-transfer level to GDSII.
“Low power is critical for our new mobile chip designs,” said Shuhei Ito, development director, Yamaha. “Because the tools in the Cadence Low-Power Solution support the Common Power Format, it allowed us to leverage advanced power management techniques, which resulted in better power and performance and shorter turnaround time for our design.”
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