Cadence & SMIC collaborate

It enables system-on-chip (SoC) developers to deliver designs with optimal power consumption, performance and area (PPA), speeding time to market to satisfy ever-increasing computer, consumer electronics, network and wireless product market requirements. The Cadence tools that provide comprehensive support from RTL-to-signoff include:

• Innovus Implementation System: A next-generation physical implementation tool that incorporates a massively parallel architecture, enabling SoC developers to deliver high-quality designs with highly competitive PPA. The tool also provides key technology for the 28nm process that supports floorplanning, placement and routing with integrated color-/pin-access-/variability-aware timing closure, and clock tree and power optimization

• Tempus Timing Signoff Solution: A comprehensive timing analysis tool that significantly reduces signoff timing closure through massively parallel processing and physically aware timing optimization while also delivering silicon-accurate timing and signal integrity analysis to ensure operational chips post-tapeout

• Voltus IC Power Integrity Solution: A full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations, accelerating IC power signoff and overall design closure

• Voltus-Fi Custom Power Integrity Solution: A SPICE-level accurate, transistor-level tool used to analyze and signoff analog, memory and custom digital IP blocks and create accurate macro models that represent the power grid view of the IP blocks during the SoC power signoff run with Voltus IC Power Integrity Solution. It supports comprehensive EM/IR design rules and requirements for the 28nm SMIC process down to the transistor device level

• Conformal Low Power Verification: Enables the creation and validation of power intent in context of the design, providing full-chip verification of power-efficient designs

• Genus Synthesis Solution: A next-generation RTL synthesis and physical synthesis engine that improves productivity challenges faced by RTL designers, delivering up to 5X faster synthesis turnaround times and scaling linearly beyond 10M instances

• Quantus QRC Extraction Solution: A next-generation parasitic extraction tool that is production proven and provides faster runtimes for single and multi-corner extraction and best-in-class accuracy versus the foundry golden

• Cadence Physical Verification System (PVS): A solution that supports full-chip and in-design signoff. PVS is tightly integrated with the Virtuoso Custom IC platform, the Innovus Implementation System and the Quantus QRC Extraction Solution to significantly reduce iterations and achieve fastest time to tapeout

• Cadence CMP Predictor: Accurately predicts multi-layer thickness and topography variability using a model-based approach developed with a model calibration tool, Cadence CMP Process Optimizer, and identifies potential problem areas (hotspots) that affect yield

• Litho Physical Analyzer (LPA): Detects manufacturability issues missed by traditional design rule checks, which helps designers improve yield during physical implementation in a fraction of the time when compared with solutions based on optical proximity correction(OPC) and lithography simulation.

“We’ve worked closely with Cadence to jointly develop the 28nm reference flow so that our customers can easily implement high-performance, low-power mobile processor chips,” said Tianshen Tang, senior vice president of Design Services at SMIC. “The integration between the innovative tools from Cadence and our 28nm technology allows design teams to improve productivity and deliver reliable designs to market faster.” “The collaboration between Cadence and SMIC enables our mutual customers to quickly deploy the advanced suite of Cadence digital implementation and signoff tools in order to achieve optimum power and a faster path to design closure,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The optimized flow enables designers to apply these innovative technologies in order to achieve optimal PPA on the SMIC 28nm process.”