Cadence C-to-Silicon Compiler Supported in Fujitsu Semiconductor’s ASIC Flow for System Realization

16th December 2010
Posted By : ES Admin
Cadence Design Systems today announced that Fujitsu Semiconductor Limited now supports the Cadence® C-to-Silicon Compiler for high-level synthesis in ASIC design flows. C-to-Silicon Compiler is the only high-level synthesis tool that embeds production RTL synthesis--Cadence Encounter® RTL Compiler--to generate implementation-ready RTL for the target application. This delivers a predictable flow from transaction-level model (TLM) to GDSII, with the ability to apply ECO patches throughout, effectively reducing System Realization time. A separate Fujitsu subsidiary has already begun using C-to-Silicon Compiler in production on a large-scale design.

“Our customers want to adopt high-level synthesis based on SystemC in order to increase their design and verification productivity, and enable wider re-use of their IP,” said Takashi Hasegawa, general manager of SoC Solutions Division, Fujitsu Semiconductor Limited. “We have carefully evaluated Cadence C-to-Silicon Compiler--which delivers the capability to handle ECOs at any time--and its contribution to rapid system development. As a result, we have decided to support its use by our customers, and we are planning to use it internally on a production design.”

C-to-Silicon Compiler raises the design abstraction level so that verification can be more productive and the design can be more readily re-used across varying configurations in end devices. The unique incremental synthesis capabilities that C-to-Silicon Compiler offers integrate tightly with Silicon Realization technologies, including

Encounter RTL Compiler, Encounter Conformal® ECO and Conformal LEC, to deliver a predictable TLM-to-GDS flow with full ECO capabilities.

“With our innovative C-to-Silicon Compiler technology, engineers can dramatically accelerate product development for various applications and derivative designs,” said Michał Siwiński, product management group director for System Realization at Cadence. “We expect Fujitsu Semiconductor to benefit significantly from the time-to-market benefits inherent in highly reusable product design and verification at a raised level of abstraction.”

The Cadence System Realization is a key component of the EDA360 vision, which emphasizes the need for rapid, applications-driven system development.

You must be logged in to comment

Write a comment

No comments

Sign up to view our publications

Sign up

Sign up to view our downloads

Sign up

30th May 2017
Germany Nuremberg
Future Surface Fleet 2017
6th June 2017
United Kingdom Portsmouth
Electronic Warfare Europe 2017
6th June 2017
United Kingdom Olympia, London
Automechanika Birmingham 2017
6th June 2017
United Kingdom NEC, Birmingham
Close Air Support 2017
7th June 2017
United Kingdom London