Aptina Picks Silicon Frontline’s Post-Layout Verification EDA Software to Eliminate Costly Prototype Builds, Improve Manufacturing Quality

20th November 2009
Posted By : ES Admin
Silicon Frontline Technology, an Electronic Design Automation (EDA) company in the post-layout verification market, announced today that Aptina, the world's foremost image sensor provider, is using Silicon Frontline’s F3D (Fast 3D) software for post-layout verification and for fast 3D extraction to improve Aptina’s image sensor design accuracy and manufacturing quality.
By using Silicon Frontline’s F3D software, Aptina’s designers are resolving a range of issues including: floating diffusion (sense node) capacitance, inter-pixel coupling, color-filter effects, impact of metal fill and signal channel mismatch without having to build costly prototypes.

With F3D, Aptina designs are released up to 4 months earlier, providing significant cost reduction and an advantageous market position.

“We are focused on being the world’s best image sensor provider,” said Roger Panicacci, VP of Product Development at Aptina. “In order to maintain our position we constantly look for design software that will improve our nanometer and A/MS design’s accuracy. Silicon Frontline’s F3D fits that bill. With it, we are able to eliminate design steps, like building prototypes to measure the accuracy and capacitance before wafer fabrication.”

“We are proud to add Aptina, an innovative leader in CMOS image sensor technology and manufacturing quality, to our list of customers,” said Yuri Feinberg, CEO, Silicon Frontline. “They are among the quality-focused customers that have picked us to improve their design productivity and manufacturing quality.”

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