Design
Implementation system achieves V0.9 certification
Cadence Design Systems has announced that its Cadence Innovus implementation system has achieved V0.9 certification for TSMC’s 10nm FinFET process and is currently on track to complete V1.0 in Q4 2015. The Innovus implementation system is a next-gen physical implementation tool that incorporates integrated signoff engines that have been validated by TSMC on high-performance reference designs, providing customers with a fast path to implemen...
Signoff tools have achieved certification from TSMC
Cadence Design Systems has announced that its digital, custom/analogue and signoff tools have achieved certification from TSMC for V0.9 of its 10nm process and are currently on track to achieve V1.0 completion by Q4 2015. The certification enables system and semiconductor companies to deliver advanced-node designs to market faster for mobile phones, tablets, application processors and high-end servers.
Comprehensive IP portfolio accelerates IoT design development
Synopsys has announced a comprehensive portfolio of IP optimised to address the security, wireless connectivity, energy-efficient and sensor processing requirements for a wide range of IoT applications such as wearables, smart appliances, metering and wireless sensor networks. The DesignWare IP portfolio for the IoT includes power- and area-efficient logic libraries, memory compilers, NVM, data converters, wired and wireless interface IP, securit...
ITTIA unites with IAR to simplify embedded data management
ITTIA has expanded support for IAR Systems' high-performance C/C++ compiler and debugger toolchain, IAR Embedded Workbench, with its flagship embedded database product. Benefits of this total solution include ease-of-use for data management with comprehensive embedded development tools.
Updated IDE increases developer productivity
Green Hills Software has announced a new release of its MULTI IDE. With this release, the company continues to evolve its software development suite with features designed to increase developer productivity and speed time-to-market.
SiP & PVS technologies enabled for dense packaging
Cadence Design Systems has announced that its Allegro System-in-Package (SiP) and Physical Verification System (PVS) implementation technologies have been enabled for TSMC’s Integrated Fan-Out (InFO) packaging technology. By providing an integrated solution that automates the Design-Rule Checking (DRC) flow, the Allegro SiP design tools and PVS enable TSMC customers to shorten the InFO design and verification cycle.
Simulation module added to automotive design software
Noise, vibration and harshness (NVH) simulation software from Bruel & Kjaer is now available to automotive designers as a module in Altair HyperWorks CAE design software. Automotive designers using Altair CAE software can now choose a module called Insight+, which enables them to listen to the sound a vehicle would make if it featured their virtual design.
Synopsys tapes out IP portfolio for TSMC 10nm FinFET process
Synopsys has announced the successful tape-out of a broad portfolio of DesignWare Interface and Foundation IP on TSMC's 10nm FinFET process, reducing risk for designers who want to take advantage of the power, area and performance improvements offered by the process.
MCU development ecosystem caters for all budgets
STMicroelectronics has introduced a MCU development ecosystem comprising prototype boards for all budgets and STM32Cube software support for the STM32L4 series now entering full production. The STM32L4 prototype boards include the fully featured STM32L476G-EVAL EVB, priced at $289, and the $19.90 STM32L476G-DISCO Discovery Kit.
TSMC certifies Synopsys design tools for 10nm FinFET technology
Synopsys has announced that TSMC has certified the Synopsys GalaxyDesign Platform digital and custom design tools for TSMC's 10nm FinFET process. The certification is based on the V0.9 version of the process and enables design engineering teams using TSMC's 10nm process to realise the power of IC Compiler II's high throughput. Tool certification of V1.0 process is targeted to be completed Q4 2015.