Design Automation

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Multi-board systems development binds design teams

The latest addition to the Mentor Graphics Xpedition platform captures the hardware description of multi-board systems, from logical system definition down to the individual PCBs, automating multi-level system design synchronisation processes to ensure team collaboration with accuracy and faster design productivity.
30th October 2014

Chip maker uses open APIs to overcome debug challenge

Chip maker SK Hynix has addressed their debug challenges by adopting the Synopsys VC Apps open application programming interfaces (APIs) to directly link their internally developed test generation technology to the Synopsys Verdi debug solution and allow their design and verification teams to customise their debug experience and boost debug productivity.
30th October 2014

RTOS supports MPLAB Harmony Framework

Express Logic’s ThreadX RTOS has been integrated into Microchip’s new MPLAB Harmony Integrated Software Framework, a set of integrated building blocks that simplify and accelerate software development for Microchip 32-bit PIC32 microcontrollers. MPLAB Harmony is a flexible, fully integrated firmware development platform for all of Microchip’s PIC32 microcontrollers.
29th October 2014


Verification IP supports 25G Ethernet specification

Cadence Design Systems has launched Verification IP (VIP) that supports the new 25-Gigabit (25G) Ethernet specification. The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes.
29th October 2014

Autonomous robots manage & analyse embedded data

ITTIA has announced that Wasserbauer has embedded ITTIA DB SQL into its next-gen robot product line, Butler. When building mission-critical embedded systems and devices, ITTIA embedded database software and services enable manufacturers to benefit from existing database skills and experience, and work with greater efficiency and accuracy.
29th October 2014

Reference kits designed for contactless payments

Reference kits designed for contactless payments
For contact and contactless payment systems, NXP Semiconductors has released Europay, MasterCard and Visa (EMVCo) compliant hardware and software design kits. An EMV Level 1 compliant software stack is offered with the OM5597/RD2612 and the OM5597/RD2663 variants for both contact and contactless payment.
29th October 2014

Characterisation solution delivers 20x performance improvement

With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros. To simplify this process, Cadence Design Systems has introduced the Virtuoso Liberate AMS characterisation solution which automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analogue paths and modelling it into a final Liberty library.
28th October 2014

Companies sign up to FPGA design software deal

Synopsys has signed a multi-year OEM agreement with Gowin Semiconductor for Synopsys Synplify Pro FPGA synthesis tools. The agreement will enable Gowin customers to improve synthesis runtimes and achieve higher quality of results for timing, area and power for Gowin GW2A/3S FPGAs.
28th October 2014

element14 aims to crowdsource the ultimate development kit

element14 aims to crowdsource the ultimate development kit
element14 has launched a global design initiative to discover the ultimate development kit for engineers and makers. The Dream Board project, live now on the element14 Community, allows users to create and brand their own virtual development kit using an interactive tool. The project will uncover the components and technologies that today’s engineers are looking for, using an innovative crowdsourcing approach.
28th October 2014

Verification IP supports popular 3D memory standards

Verification IP supports popular 3D memory standards
Cadence's Verification IP (VIP) supports all popular 3D memory standards, including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS). The portfolio of memory VIP allows designers to accelerate the verification of memory interfaces and achieve earlier SoC verification closure for compute server applications, mobile devices, high-performance graphics and network applications.
28th October 2014


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