Design

Displaying 1 - 10 of 4902

Digital tools achieve Samsung process technology certification

Digital tools achieve Samsung process technology certification
The custom/analogue tools and full-flow digital and signoff tools from Cadence Design Systems have achieved certification for the process design kit (PDK) and foundation library for the Samsung Electronics’ 28nm fully depleted silicon-on-insulator (FDS), also known as FD-SOI, process technology.
30th May 2017

Development package for complex Windows software

Development package for complex Windows software
PEAK-System has extended the development package PCAN-Developer and the included PCAN-API programming interface with CAN FD. Therefore Windows applications can now be created with CAN and CAN FD connections. Specifically, the API provides extensive programme libraries via 32-bit and 64-bit interface DLLs, as well as header files and sample projects for the programming languages C, C++, and Delphi. In the near future,.NET-compatible languages such as C#, C++/CLR and Visual Basic will be added.
26th May 2017

Design tools cover FPGAs, programmable logic

Design tools cover FPGAs, programmable logic
Quartus II, Vivado and ModelSim design tools and the development of designs using VHDL are at the heart of LDD Technology’s electronic design services. The company has extensive FPGA and programmable logic design expertise and in-depth knowledge of devices from major semiconductor manufacturers including Altera and Xilinx.
26th May 2017


Duo expand flow control tool offering for mutual customers

Mentor, a Siemens business, has announced the addition of the Calibre DFM Explorer flow control tool, created by Mentor for use by Samsung Electronics and its foundry customers as an extension to the complete suite of Calibre design for manufacturing (DFM) products that are part of Samsung’s mandatory sign-off requirements. The Calibre DFM Explorer tool is used by customers who have designs that require DFM applications running across multiple CPUs to achieve target turnaround times.
25th May 2017

Improved design supports Samsung's latest foundry processes

Synopsys has announced that Samsung Electronics has enabled the Synopsys Design Platform for Samsung's 8LPP (Low-Power Plus) and 7LPP process technologies. Samsung's 8LPP, a process derivative of 10LPP, offers smaller area when compared to 10LPP with minimal impact to the 10-nm design methodology. Synopsys Design Platform, silicon-proven at 10LPP, is being confidently deployed by early adopters of the 8LPP and 7LPP processes.
25th May 2017

Digital and signoff tools enabled on process technologies

Digital and signoff tools enabled on process technologies
Cadence Design Systems has announced that its digital, signoff and custom/analogue tools are enabled on Samsung Electronics’ 7LPP and 8LPP process technologies. The 7LPP and 8LPP process technologies continue to deliver power, performance and area optimisations with additional scaling benefits over previous generations of advanced FinFET nodes, and customers can begin working on early designs using these next-gen technologies.
25th May 2017

Multi-protocol IP reduces power and area by over 35%

Multi-protocol IP reduces power and area by over 35%
  Suitable for high-performance computing applications including machine learning and artificial intelligence, Synopsys has announced its new DesignWare Multi-Protocol 25G PHY IP. The PHY IP gives designers the flexibility to efficiently integrate multiple protocols including PCI Express 4.0, 25G Ethernet, SATA and CCIX into system-on-chips (SoCs) targeting the 7 and 16nm FinFET processes.
24th May 2017

Advanced formal-based technologies address RTL signoff requirements

Cadence Design Systems has announced the expansion of its JasperGold Formal Verification Platform with the introduction of the JasperGold Superlint and Clock Domain Crossing (CDC) Apps, advanced formal-based technologies that address register-transfer level (RTL) signoff requirements. The Superlint and CDC Apps bring the power of JasperGold formal technology to the RTL designer’s desktop.
24th May 2017

Evaluation kit enables simplified design

Evaluation kit enables simplified design
Cypress Semiconductor has introduced a new kit to evaluate its energy harvesting PMIC family. The CYALKIT-E04 Evaluation Kit providea developers with an easy-to-use platform to create battery-free systems using a solar-powered module or to support battery-life extension, and can be used for evaluation of diverse power management functions used for wireless sensor nodes. The kit can be used with BLE wireless connectivity solutions from Cypress for IoT applications.
23rd May 2017

OCP specification approved for carrier grade CG-OpenRack-19

OCP specification approved for carrier grade CG-OpenRack-19
Provider of computing solutions that drive data-to-decision applications across industries, ADLINK Technology, has introduced its OpenSled specification, contributing to the evolution of the next-gen of appliances that fit into the Open Compute Project (OCP) CG-OpenRack-19 specification. Standards development around networking and communications frameworks has become increasingly important with the growing utilisation of edge, cloud and fog computing architectures that support the OT/IT/CT convergence critical to driving business value.
23rd May 2017


Design documents


Sign up to view our publications

Sign up

Sign up to view our downloads

Sign up

Future Surface Fleet 2017
6th June 2017
United Kingdom Portsmouth
Electronic Warfare Europe 2017
6th June 2017
United Kingdom Olympia, London
Automechanika Birmingham 2017
6th June 2017
United Kingdom NEC, Birmingham
Close Air Support 2017
7th June 2017
United Kingdom London
All about IoT sensors
8th June 2017
United Kingdom London