Design

Displaying 1 - 10 of 4494

ARM Cycle Models enable cache coherent interconnect IP

Arteris announces that it has used ARM Cycle Models for use in hardware and performance verification of its Ncore Cache Coherent Interconnect IP.
26th May 2016

Mentor platform chosen for analogue & RF circuit verification

Mentor platform chosen for analogue & RF circuit verification
Mentor Graphics has announced that Silicon Labs has selected the Analog FastSPICE (AFS) platform for circuit verification and device noise analysis of its complex pre- and post-layout analogue circuits. Silicon Labs is using AFS to analyse PLLs, data converters, wired and wireless transceivers and other specialised high performance analogue and RF circuits.
26th May 2016

Expanded toolchain creates new possibilities

Opening up a range of new options for using the latest CAN FD data bus standard in rapid control prototyping (RCP), dSPACE has extended its tool chain.
25th May 2016


Eaton announces Intelligent Power Manager software version 1.52

Eaton announced the global launch of Intelligent Power Manager software version 1.52, which can be integrated with the VMware vRealize Operations platform. Now, datacentre and operations managers can use Eaton’s Intelligent Power Manager software and Infrastructure Management Pack to manage the health, risk and efficiency of their power devices and equipment similarly to how they use VMware vRealize Operations to manage their information technology devices in a software-defined datacentre.
25th May 2016

Cache coherent subsystem verification for Arteris' Ncore interconnect

Synopsys has announced the availability of the industry's first cache coherent subsystem verification solution for Arteris' Ncore interconnect. The Arteris Ncore interconnect is a configurable distributed heterogeneous cache coherent interconnect that enables SoC teams to efficiently design customised, fully coherent systems.
25th May 2016

Arduino shield speeds stepper motor system prototyping

Arduino shield speeds stepper motor system prototyping
Supporting the evaluation of motor driver devices as well as enabling, facilitating and accelerating customers' development, ROHM Semiconductor announces an Arduino-based evaluation kit. Designed as a ‘shield’ to plug directly into the Arduino main board, the EVK integrates ROHM's HTSSOP-B28 packaged stepper motor drive IC and complements the company’s support ecosystem, allowing engineers to rapidly prototype their stepper motor systems.
24th May 2016

Improving productivity, security & user experience for field workers

Bittium and Getac have established a partnership to improve productivity, security and user experience for field workers in the most demanding environments. Bittium's SafeMove Mobile VPN and Analytics software will now be offered to all Getac’s rugged tablets and notebooks as an option across Europe from May 2016 onwards.
24th May 2016

Accurate thermal & air flow simulations for electromagnetic systems

Computer Simulation Technology (CST) has unveiled its upcoming Conjugate Heat Transfer (CHT) solver of CST STUDIO SUITE at IMS 2016, booth #739. The CHT solver offers accurate thermal and air flow simulations for electromagnetic systems.
24th May 2016

CST releases free EM simulation package for students

Computer Simulation Technology (CST) has announced the newest release of CST STUDIO SUITE – Student Edition at IMS 2016, booth #739. The student edition is a special free version of its flagship EM simulation package specifically for students. This release adds a low-frequency solver especially suitable for learning about eddy currents.
24th May 2016

Reduce semiconductor process development time

Synopsys has announced a pre-wafer simulation solution to help semiconductor manufacturers reduce process node development time. The solution provides a comprehensive process, transistor and circuit simulation flow that enables technology development and design teams to evaluate various transistor and process options using a design technology co-optimisation methodology that starts in the pre-wafer research phase.
24th May 2016


Design documents


Sign up to view our publications

Sign up

Sign up to view our downloads

Sign up

 

WEBENCH® Designer