Design Automation

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Verification technology simplifies electronic schematics

Verification technology simplifies electronic schematics
  In an effort to simplify the visual inspection and debugging process of electronic schematics, Altium and Valydate have partnered, integrating the ValydateVERA design analysis and verification tool into the Altium Designer.  
28th January 2015

Open code generation tool cuts design time & effort

Open code generation tool cuts design time & effort
During the last 10 years, model-based design environments have proved to be a significant innovation for developers of embedded control software. However, in safety-critical domains such as avionics, rail, and automotive systems, current off-the-shelf approaches raise several issues with respect to software verification.
27th January 2015

How Flash is transforming the data centre one tier at a time

How Flash is transforming the data centre one tier at a time
Flash is quickly becoming an integral part of daily operations at large data centres. As customers seek to address the 'mismatch' between increasing processor speeds and storage based on mechanically-driven HDDs, they are turning to flash, valuing the speed and performance associated with it. By Chris Gale, European Marketing Director, SanDisk.
27th January 2015


16-bit MCUs added to code development plug-in tool

16-bit MCUs added to code development plug-in tool
Microchip has extended its MPLAB Code Configurator Plug-In to support 16-bit PIC MCUs. In addition to the 8-bit devices already supported, Microchip has added support for more than 50 16-bit devices into the latest release of the MPLAB Code Configurator, a code development tool aiming to enable developers to enhance the design experience with faster application development.
26th January 2015

Integrated run-time software now supports Atmel, ST & TI

Introduced with support for the Renesas RZ/A1-based RSK board, Express Logic has expanded its support for the X-Ware Platform to include boards from Atmel, STMicroelectronics and Texas Instruments. The target-specific, integrated run-time software combines all X-Ware components (ThreadX, NetX, USBX, FileX, GUIX and TraceX) pre-ported and fully integrated for use on specific development boards.
26th January 2015

First wireless Arduino programming app for Windows

First wireless Arduino programming app for Windows
The Windows Bean Loader has been launched by Punch Through Design, hailed as the first-ever wireless Arduino programming app for Windows users. This enables Windows-based developers and hobbyists to easily upload code to their LightBlue Bean MCU board and experience the power of BLE, without cables or a physical connection to the LightBlue Bean.
26th January 2015

Libraries meet demands of fabless IC suppliers

Dolphin Integration’s sponsored offering at TSMC 55nm uLP and uLPeF meets the demands of fabless IC suppliers for solutions that enable high performance SoCs with a low power consumption. A number of the company’s products complement the 55nm uLP/uLPeF.
26th January 2015

Signoff tools reduce 28nm SoC time to tapeout by 33%

United Microelectronics (UMC) used Cadence Design Systems’ implementation and signoff tools to produce a silicon-ready 28nm ARM Cortex-A7 MPCore-based SoC, Cadence has announced. With the Cadence solution, UMC reduced the time to tapeout by 33% compared with its previous solution, and achieved performance of 1.7GHz.
26th January 2015

DesignWare HDMI IP receives HDMI 2.0 certification

The DesignWare HDMI 2.0 TX and RX controller and PHY IP, developed by Synopsys, have been certified by an HDMI authorised testing centre. The company’s HDMI 2.0 IP with Elliptic Technologies' HDCP embedded security module also achieved HDCP 2.2 certification, enabling the highest content protection over the HDMI 2.0 interface for HD multimedia SoCs.
23rd January 2015

Verification IP supports JEDEC UFS, eMMC & MIPI UniPro

Synopsys has expanded its memory Verification IP portfolio to include key titles for the mobile industry. Synopsys memory VIP is based on a native SystemVerilog architecture to enable enhanced ease of use, integration and configurability. With these advanced features, project teams using the JEDEC UFS, MIPI UniPro and JEDEC eMMC protocols can further accelerate verification closure of mobile block, subsystem and SoC designs.
23rd January 2015


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